M32C83T datasheet(360/527 Pages) RENESAS

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Page 337

22. CAN Module

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22.1.9 CAN0 Receive Error Count Register (C0REC Register)

CAN0 Receive Error Count Register

Symbol

Address

After Reset(1)

C0REC

020B16

0016

Function

Counter Value of Receive Error

NOTES:

1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and

supplying a clock to the CAN module after reset.

Figure 22.11 C0REC Register

In an error active or an error passive state, a count value of the reception error is stored into the

C0REC register. The counter is decremented when the CAN module has received data as expected

or is incremented when a receive error occurs.

The C0REC register is set to 127 when the C0REC register is 128 (error passive state) or more and

the CAN module has received as expected.

In a bus-off state, an indeterminate value is stored into the C0REC register. The C0REC register is

set to "0016" when the CAN module is placed in an error active state again.

22.1.10 CAN0 Baud Rate Prescaler (C0BRP Register)

CAN0 Baud Rate Prescaler

Symbol

Address

After reset(1)

C0BRP

021716

0116

Function

Setting Range

0116 to FF16(2)

If setting value is n, the CPU clock is divided

by (n+1).

NOTES:

1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and

supplying a clock to the CAN module after reset.

2. Do not set to "0016" (divide-by-1).

Figure 22.12 C0BRP Register

The C0BRP register determines the Tq clock cycle of the CAN bit timing. The baud rate is obtained

from Tq clock cycle x Tq per bit.

Tq clock cycle = (BRP+1) / f1

Baud rate =

Tq per bit = SS + PTS + PBS1 + PBS2

Tq: Time quantum

BRP: Setting value of the C0BRP register; 1-255

SS: Synchronization Segment; 1 Tq

PTS: Propagation Time Segment; 1 to 8 Tq

PBS1: Phase Buffer Segment 1; 2 to 8 Tq

PBS2: Phase Buffer Segment 2; 2 to 8 Tq

Tq clock cycle x Tq per bit

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