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M32C83T Datasheet(PDF) 367 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 367 Page - Renesas Technology Corp |
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367 / 527 page ![]() Page 344 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 22. CAN Module ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M CAN0 Global Mask Register Standard ID1(1) CAN0 Local Mask Register A Standard ID1(1) CAN0 Local Mask Register B Standard ID1(1) Symbol Address After Reset(2) C0GMR1 022916 XX00 00002 C0LMAR1 023116(3) XX00 00002 C0LMBR1 023916(4) XX00 00002 RW Standard ID0 0: No ID is checked 1: ID is checked Standard ID1 Standard ID2 Standard ID3 Standard ID4 Standard ID5 SID0M SID1M SID2M SID3M SID4M SID5M (b7 - b6) Bit Name Function Bit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW RW NOTES: 1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1". 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 3. The C0LMAR1 register shares the same address with the C0MCTL1 register. 4. The C0LMBR1 register shares the same address with the C0MCTL9 register. b7 b6 b5 b4 b3 b2 b1 b0 CAN0 Global Mask Register Extended ID0(1) CAN0 Local Mask Register A Extended ID0(1) CAN0 Local Mask Register B Extended ID0(1) Symbol Address After Reset(2) C0GMR2 022A16 XXXX 00002 C0LMAR2 023216(3) XXXX 00002 C0LMBR2 023A16(4) XXXX 00002 RW EID14M EID15M EID16M EID17M (b7 - 4) Extended ID14 0: No ID is checked 1: ID is checked Extended ID15 Extended ID16 Extended ID17 Bit Name Function Bit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW NOTES: 1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1". 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 3. The C0LMAR2 register shares the same address with the C0MCTL2 register. 4. The C0LMBR2 register shares the same address with the C0MCTL10 register. b7 b6 b5 b4 b3 b2 b1 b0 Figure 22.18 C0GMR1, C0LMAR1 and C0LMBR1 Registers and C0GMR2, C0LMAR2 and C0LMBR2 Registers |
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