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M32C83T Datasheet(PDF) 368 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 368 Page - Renesas Technology Corp |
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368 / 527 page ![]() Page 345 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 22. CAN Module ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M CAN0 Global Mask Register Extended ID1(1) CAN0 Local Mask Register A Extended ID1(1) CAN0 Local Mask Register B Extended ID1(1) Symbol Address After Reset(2) C0GMR3 022B16 0016 C0LMAR3 023316(3) 0016 C0LMBR3 023B16(4) 0016 EID6M EID7M EID8M EID9M EID10M EID11M EID13M EID12M Extended ID6 0: No ID is checked 1: ID is checked Extended ID7 Extended ID8 Extended ID9 Extended ID10 Extended ID11 Extended ID12 Extended ID13 Bit Name Function Bit Symbol b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW NOTES: 1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1". 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 3. The C0LMAR3 register shares the same address with the C0MCTL3 register. 4. The C0LMBR3 register shares the same address with the C0MCTL11 register. CAN0 Global Mask Register Extended ID2(1) CAN0 Local Mask Register A Extended ID2(1) CAN0 Local Mask Register B Extended ID2(1) Symbol Address After Reset(2) C0GMR4 022C16 XX00 00002 C0LMAR4 023416(3) XX00 00002 C0LMBR4 023C16(4) XX00 00002 EID0M EID1M EID2M EID3M EID4M EID5M (b7 - b6) Extended ID0 0: No ID is checked 1: ID is checked Extended ID1 Extended ID2 Extended ID3 Extended ID4 Extended ID5 Bit Name Function Bit Symbol Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RW RW RW RW RW RW RW NOTES: 1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1". 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 3. The C0LMAR4 register shares the same address with the C0MCTL4 register. 4. The C0LMBR4 register shares the same address with the C0MCTL12 register. b7 b6 b5 b4 b3 b2 b1 b0 Figure 22.19 C0GMR3, C0LMAR3 and C0LMBR3 Registers and C0GMR4, C0LMAR4 and C0LMBR4 Registers |
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