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M32C83T Datasheet(PDF) 369 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 369 Page - Renesas Technology Corp |
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369 / 527 page  Page 346 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 22. CAN Module ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M 22.1.16 CAN0 Message Slot i Control Register (C0MCTLi Register) (i=0 to 15) CAN0 Message Slot i Control Register (i=0 to 15)(1) Symbol Address After Reset (2) C0MCTL0 to C0MCTL3 023016(3), 023116(3), 023216(3), 023316(3) 0000 00002 C0MCTL4 to C0MCTL7 023416(3), 023516, 023616, 023716 0000 00002 C0MCTL8 to C0MCTL11 023816(3), 023916(3), 023A16(3), 023B16(3) 0000 00002 C0MCTL12 to C0MCTL15 023C16(3), 023D16, 023E16, 023F16 0000 00002 When receive, NEWDATA When transmit, SENTDATA When receive, INVALDATA When transmit, TRMACTIVE MSGLOST REMACTIVE RSPLOCK REMOTE TRMREQ RECREQ Receive Complete Flag Transmit Complete Flag Receiving Flag Transmitting Flag In modes other than BasicCan mode 0: Data frame 1: Remote frame In BasicCan mode 0: Receives the data frame (status) 1: Receives the remote frame (status) 0: Enables automatic answering of the remote frame 1: Disables automatic answering of the remote frame 0: Transmits/receives the data frame 1: Transmits/receives the remote frame 0: No request to receive the frame 1: Request to receive data 0: No request to transmit the frame 1: Request to transmit data Overwrite Flag Remote Frame Transmit/Receive Status Flag Automatic Answering Disable Mode Select Bit Remote Frame Set Bit Receive Request Bit Transmit Request Bit 0: No overrun error occurs 1: Overrun error occurs (Note 4) 0: Not transmitted(4) 0: Not received(4) 1: Transmit complete 1: Receive complete When transmitting When receiving 0: Stops transmitting 0: Stops receiving 1: Transmits 1: Stores received data When transmitting When receiving Bit Name Function Bit Symbol b7 b6 b5 b4 b3 b2 b1 b0 RW RW RO RW RO RW RW RW RW NOTES: 1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1". 2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. 3. The C0MCTL0 to C0MCTL4 registers each share addresses with the C0MAR0 to C0MAR4 registers. 4. Each bit can be set to "0" by program. If it is set to "1", the value before setting to "1" remains. Figure 22.20 C0MCTL0 to C0MCTL15 Registers Table 22.4 C0MCTLi Register (i= 0 to 15) Settings and Transmit/Receive Mode Settings for the C0MCTLi Register TRMREQ RECREQ REMOTE RSPLOCK REMACTIVE MSGLOST TRMACTIVE SENTDATA Transmit/Receive Mode INVALDATA NEWDATA 0 000 0 0 0 0 No frame is transmitted or received 0 1 0 0 0 0 0 0 Data frame is received 0 1 1 1 0 0 0 0 Remote frame is received or (The data frame is transmitted 0 after receiving the remote frame.) 1 0 0 0 0 0 0 0 Data frame is transmitted 1 010 0 0 0 0 Remote frame is transmitted (The data frame is received after transmitting the remote frame) |
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