M32C83T datasheet(128/527 Pages) RENESAS

128 / 527 page

Page 105

10. Interrupts

)

(

External Interrupt Request Cause Select Register

Symbol

Address

After Reset

IFSR

031F16

0016

INT0 Interrupt Polarity

Select Bit(1)

INT1 Interrupt Polarity

Select Bit(1)

INT2 Interrupt Polarity

Select Bit(1)

INT3 Interrupt Polarity

Select Bit(1)

INT4 Interrupt Polarity

Select Bit(1)

INT5 Interrupt Polarity

Select Bit(1)

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

Bit Name

Bit

Symbol

Function

NOTES:

1.Set this bit to "0" to select level sensitive.

When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge).

UART1, UART4

Interrupt Cause Select

Bit

UART0, UART3

Interrupt Cause Select

Bit

0 : One edge

1 : Both edges

IFSR3

IFSR4

IFSR5

IFSR6

IFSR0

IFSR2

IFSR1

IFSR7

0 : UART3 bus conflict, start condition

detect, stop condition detect, fault

error detect

1 : UART0 bus conflict, start condition

detect, stop condition detect, fault

error detect

0 : UART4 bus conflict, start condition

detect, stop condition detect, fault

error detect

1 : UART1 bus conflict, start condition

detect, stop condition detect, fault

error detect

______

10.7 INT Interrupt

______

External input generates the INTi interrupt (i = 0 to 5). The LVS bit in the INTiIC register selects either edge

sensitive triggering to generate an interrupt on any edge or level sensitive triggering to generate an inter-

rupt at an applied signal level. The POL bit in the INTiIC register determines the polarity.

With an edge sensitive triggering, when the IFSRi bit in the IFSR register is set to "1" (both edges), an

interrupt occurs on both rising and falling edges of the external input. If the IFSRi bit is set to "1", set the

POL bit in the corresponding register to "0" (falling edge).

_______

With a level sensitive triggering, set the IFSRi bit to "0" (single edge). When the INTi pin input level reaches

the level set in the POL bit, the IR bit in the INTiIC register is set to "1". The IR bit remains set to "1" even

_______

if the INTi pin level is changed. The IR bit is set to "0" when the INTi interrupt is acknowledged or when "0"

is written by program.

Figure 10.10 shows the IFSR register.

Figure 10.10 IFSR Register

M32C83T Datasheet(PDF) 128 Page - Renesas Technology Corp

M32C83T Datasheet(HTML) 128 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL