M32C83T datasheet(130/527 Pages) RENESAS

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Page 107

10. Interrupts

)

(

AIER0

AIER1

AIER2

Address Match

Interrupt 0 Enable Bit

Address Match

Interrupt 1 Enable Bit

Address Match

Interrupt 2 Enable Bit

Address Match

Interrupt 3 Enable Bit

AIER3

(b7 - b4)

Function

Address Match Interrupt Enable Register

0 : Disables the interrupt

1 : Enables the interrupt

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

Bit Name

Bit

Symbol

Address

After Reset

AIER

000916

XXXX 00002

0 : Disables the interrupt

1 : Enables the interrupt

0 : Disables the interrupt

1 : Enables the interrupt

0 : Disables the interrupt

1 : Enables the interrupt

10.10 Address Match Interrupt

The address match interrupt occurs immediately before executing an instruction that is stored into an ad-

dress indicated by the RMADi register (i=0 to 3). The address match interrupt can be set in four addresses.

The AIERi bit in the AIER register determines whether the interrupt is enabled or disabled. The I flag and

IPL do not affect the address match interrupt.

Figure 10.12 shows registers associated with the address match interrupt.

Set the starting address of an instruction in the RMADi register. The address match interrupt does not

occur when a table data or addresses other than the starting address of the instruction is set.

Figure 10.12 AIER Register and RMAD0 to RMAD3 Registers

Address Match Interrupt Register i

Function

Setting Range

Symbol

Address

After Reset

RMAD0

001216 - 001016

00000016

RMAD1

001616 - 001416

00000016

RMAD2

001A16 - 001816

00000016

RMAD3

001E16 - 001C16

00000016

00000016 to FFFFFF16

Addressing Register for the Address Match Interrupt

b23

b16 b15

b8 b7

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