M32C83T datasheet(134/527 Pages) RENESAS

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Page 111

11. Watchdog Timer

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11. Watchdog Timer

The watchdog timer detects a program which is out of control. The watchdog timer contains a 15-bit counter

which is decremented by the CPU clock that the prescaler divides. The CM06 bit in the CM0 register

determines whether the watchdog timer interrupt request or reset is generated when the watchdog timer

underflows. The CM06 bit can be set to "1" (reset) only. Once the CM06 bit is set to "1", it cannot be

changed to "0" ( watchdog timer interrupt) by program. The CM06 bit is set to "0" only after reset.

When the main clock, on-chip oscillator clock, or the PLL clock runs as the CPU clock, the WDC7 bit in the

WDC register determines whether the prescaler divides by 16 or by 128. When the sub clock runs as the

CPU clock, the prescaler divides by 2 regardless of the WDC7 bit setting. Watchdog timer cycle is calcu-

lated as follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.

When the main clock, on-chip oscillator clock, or PLL clock is selected as the CPU clock:

Watchdog timer cycle =

When the sub clock is selected as the CPU clock,

Watchdog timer cycle =

For example, if the CPU clock frequency is 30MHz and the prescaler divides by 16, watchdog timer cycle is

approximately 17.5 ms.

The watchdog timer is reset when the WDTS register is set and when a watchdog timer interrupt request is

generated. The prescaler is reset only when the microcomputer is reset. Both watchdog timer and prescaler

stop after reset. They begin counting when the WDTS register is set.

Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the

beginning of the watchdog timer interrupt routine.

The watchdog timer and prescaler stop in stop mode, wait mode and hold state. They resume counting

from the value held when the mode or state is exited.

Figure 11.1 shows a block diagram of the watchdog timer. Figure 11.2 shows registers associated with the

watchdog timer.

Divide by 16 or 128 prescaler x counter value of watchdog timer (32768)

CPU clock

Divided by 2 prescaler x counter value of watchdog timer (32768)

CPU clock

Watchdog Timer

Interrupt Request

CM06

Write to WDTS Register

Watchdog Timer

Set to

7FFF16

1/128

1/16

CM07 = 0

WDC7 = 1

CM07 = 0

WDC7 = 0

CM07 = 1

1/2

Prescaler

HOLD Signal

Reset

CPU Clock

CM06, CM07 : Bits in CM0 register

WDC7 : Bit in WDC register

Internal Reset Signal

Figure 11.1 Watchdog Timer Block Diagram

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