M32C83T datasheet(136/527 Pages) RENESAS

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Page 113

11. Watchdog Timer

)

(

Symbol

Address

After Reset

CM0

000616

0000 X0002

System Clock Control Register 0(1)

CM00

CM01

CM02

(b3)

Clock Output Function

Select Bit(2)

In Wait Mode,

Peripheral

Function Clock Stop Bit

Port XC Switch Bit

Main Clock (XIN-XOUT)

Stop Bit(5)

CM04

CM05

CM06

CM07

Function

Bit Name

Bit

Symbol

0 : Main clock oscillates

1 : Main clock stops(6)

0 0 : I/O port P53

0 1 : Outputs fC

1 0 : Outputs f8

1 1 : Outputs f32

0 : I/O port function

1 : XCIN-XCOUT oscillation function(4)

Watchdog Timer

Function Select Bit

System Clock Select Bit(8)

0: Clock selected by the CM21 bit

divided by MCD register setting

1: Sub clock

0 : Watchdog timer interrupt

1 : Reset(7)

NOTES:

1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable).

2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 to CM00 bits to

"002". When the PM15 to PM14 bits in the PM1 register is set to "012" (ALE output to P53), set the

CM01 to CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 to CM00

bits) in microprocessor or memory expansion mode, and the CM01 to CM00 bits are set to "002", an

"L" signal is output from port P53 (port P53 does not function as an I/O port).

3. fc32 does not stop. When the CM02 bit is set to "1", the PLL clock cannot be used in wait mode.

4. When setting the CM04 bit to "1" (XCIN-XCOUT oscillation), set the PD8_7 to PD8_6 bits to "002" (with

port P87 and P86 input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up).

5. When entering the low-power consumption mode or on-chip oscillator low-power consumption mode,

the CM05 bit stops the main clock. The CM05 bit cannot detect whether the main clock stops or not.

To stop the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable sub clock

oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock). When the

CM05 bit is set to "1", XOUT becomes "H". The built-in feedback resistor remains on. XIN is pulled up

to XOUT ("H" level) via the feedback resistor.

6. When the CM05 bit is set to "1", the MCD register is set to "0816" (divide-by-8 mode). In on-chip

oscillation mode, the MCD register is not divided by eight even if the CM05 bit terminates XIN-XOUT.

7. Once the CM06 bit is set to "1", it cannot be set "0" by program.

8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0".

After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1".

Do not set the CM07 bit and CM04 or CM05 bits simultaneously.

b1 b0

0 : Peripheral clock does not stop in

wait mode

1 : Peripheral clock stops in wait

mode(3)

Reserved Bit

Set to "1"

Figure 11.3 CM0 Register

M32C83T Datasheet(PDF) 136 Page - Renesas Technology Corp

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