M32C83T datasheet(138/527 Pages) RENESAS

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Page 115

12. DMAC

)

(

DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to 3) or by using an interrupt

request, generated by the functions determined by the DSEL 4 to DSEL0 bits in the DMiSL register, as a

DMA request. Unlike interrupt requests, the I flag and interrupt control register do not affect DMA. There-

fore, a DMA request can be acknowledged even if an interrupt is disabled and cannot be acknowledged. In

addition, the IR bit in the interrupt control register does not change when a DMA request is acknowledged.

Table 12.1 DMAC Specifications

Item

Specification

Channels

4 channels (cycle-steal method)

Transfer Memory Space

• From a desired address in a 16M-byte space to a fixed address in a

16M-byte space

• From a fixed address in a 16M-byte space to a desired address in a

16M-byte space

Maximum Bytes Transferred

128K bytes (when a 16-bit data is transferred) or 64K bytes (when an 8-

bit data is transferred)

DMA Request Factors(1)

________

Falling edge or both edges of input signals to the INT0 to INT3 pins

Timer A0 to timer A4 interrupt requests

Timer B0 to timer B5 interrupt requests

UART0 to UART4 transmit and receive interrupt requests

A/D conversion interrupt request

Intelligent I/O interrupt request

CAN interrupt request

Software trigger

Channel Priority

DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has highest priority)

Transfer Unit

8 bits, 16 bits

Destination Address

Forward/fixed (forward and fixed directions cannot be specified when

specifying source and destination addresses simultaneously)

Transfer Mode Single Transfer Transfer is completed when the DCTi register (i = 0 to 3) is set to "000016"

Repeat Transfer When the DCTi register is set to "000016", the value of the DRCi register

is reloaded into the DCTi register and the DMA transfer is continued

DMA Interrupt Request Generation Timing When the DCTi register changes "000116" to "000016"

DMA Startup

Single Transfer DMA starts when a DMA request is generated after the DCTi register is

set to "000116" or more and the MDi1 to MD0 bits in the DMDj register (j

= 0 to 1) are set to "012" (single transfer)

Repeat Transfer DMA starts when a DMA request is generated after the DCTi register is

set to "000116" or more and the MDi1 to MDi0 bits are set to "112" (re-

peat transfer)

DMA Stop

Single Transfer DMA stops when the MDi1 to MDi0 bits are set to "002" (DMA disabled)

or when the DCTi register is set to "000016" (0 DMA transfer) by DMA

transfer or write

Repeat Transfer DMA stops when the MDi1 to MDi0 bits are set to "002" or when the

DCTi register is set to "000016" and the DRCi register set to "000016"

Reload Timing to the DCTi

When the DCTi register is set to "000016" from "000116" in repeat trans-

or DMAi Register

fer mode

DMA Transfer Cycles

Minimum 3 cycles between SFR and internal RAM

NOTES:

1. The IR bit in the interrupt control register does not change when a DMA request is acknowledged.

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