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M32C83T Datasheet(PDF) 156 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 156 Page - Renesas Technology Corp |
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156 / 527 page ![]() Page 133 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 14. Timer ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M 14. Timer The microcomputer has eleven 16-bit timers. Five timers A and six timers B have different functions. Each timer operates independently. The count source for each timer is the clock for timer operations including counting and reloading, etc. Figures 14.1 and 14.2 show block diagrams of timer A and timer B configuration. CST 00: Timer mode 10: One-shot timer mode 11: PWM mode 01: Event counter mode TA0IN TA1IN TA2IN TA3IN TA4IN Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 f1 f8 f2n fC32 Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Noise filter Noise filter Noise filter Noise filter Noise filter 1/8 f1 f8 Main clock, PLL clock or On-chip oscillator clock 1/2n (Note 1) 00 01 10 11 TCK1 to TCK0 00: Timer mode 10: One-shot tiemr mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 01: Event counter mode 01: Event counter mode 01: Event counter mode 01: Event counter mode TCK1 to TCK0 TCK1 to TCK0 TCK1 to TCK0 TCK1 to TCK0 TMOD1 to TMOD0 TMOD1 to TMOD0 TMOD1 to TMOD0 TA0TGH to TA0TGL Timer B2 overflow or underflow 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 CST: Bit in TCSPR register TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register TAiGH to TAiGL: Bits in ONSF register or TRGSR register (i=1 to 4) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). f2n TA1TGH to TA1TGL TA2TGH to TA2TGL TA3TGH to TA3TGL TA4TGH to TA4TGL TMOD1 to TMOD0 TMOD1 to TMOD0 1/32 fC32 XCIN Set the CPSR bit in the CPSRF register to "1" Reset Clock prescaler Figure 14.1 Timer A Configuration |
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