 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
M32C83T Datasheet(PDF) 196 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
M32C83T Datasheet(HTML) 196 Page - Renesas Technology Corp |
|
|
196 / 527 page  Page 173 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 16. Serial I/O ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M m : setting value of UiBRG register RxDi Receive Control Circuit Transmit Control Circuit 1 / (m+1) 1/16 1/16 1/2 UiBRG Register Clock Synchronous Type (when internal clock is selected) Clock Asynchronous Receive Clock Synchronous Type Clock Synchronous Type Clock Synchronous Type (when internal clock is selected) Clock Synchronous Type (when external clock is selected) Receive Clock Transmit Clock CLKi CTSi / RTSi f1 f8 f2n(2) Vss CTSi TxDi RxD Polarity Switching Circuit TxD Polarity Switching Circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CLK Polarity Switching Circuit CKDIR Inside Outside Selecting Clock Source Transmit/ Receive Unit (Note 1) NOTES: 1. P70 and P71 are ports for the N-channel open drain output, but not for the CMOS output. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 01 10 0 00 1 CKPOL CLK1 to CLK0 010, 100, 101, 110 010, 100, 101, 110 001 001 Clock Asynchronous Transmit SMD2 to SMD0 CKDIR CRD CRD 1 1 0 0 RTSi CRS 0 1 Clock Asynchronous Type (8 bits) Clock Synchronous Type Clock Asynchronous Type (7 bits) SP SP PAR Clock Synchronous Type Clock Synchronous Type Low-order bits of data bus TxDi UARTi Transmit Register PAR disabled PAR enabled D8 D7 D6 D5 D4 D3 D2 D1 D0 UiTB Register Clock Synchronous Type UiRB Register UARTi Receive Register 2SP 1SP RxDi D7 D6 D5 D4 D3 D2 D1 D0 D8 000 0 000 SP SP PAR 0 Inverse No inverse Error Signal Output Circuit RxD Data Inverse Circuit Error Signal Output enable Error Signal Output disable Inverse No inverse Logic Inverse Circuit + MSB/LSB Conversion Circuit Logic Inverse Circuit + MSB/LSB Conversion Circuit PAR enabled PAR disabled Clock Synchronous Type TxD Data Inverse Circuit SP: Stop bit PAR: Parity bit i=0 to 4 SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in UiC0 register UiERE: Bit in UiC1 register 0 1 IOPOL 1 0 PRYE 0 1 Clock Asynchronous Type (9 bits) Clock Synchronous Type Clock Asynchronous Type (8 bits) Clock Asynchronous Type Clock Asynchronous Type (9 bits) Clock Asynchronous Type (7 bits) 0 1 1 1 SMD2 to SMD0 STPS 0 Clock Asynchronous Type (7 bits) Clock Asynchronous Type (8 bits) Clock Asynchronous Type (8 bits) Clock Asynchronous Type (9 bits) Clock Asynchronous Type (7 bits) 1SP 2SP 0 1 STPS PRYE 0 1 Clock Asynchronous Type 1 Clock Asynchronous Type (9 bits) 11 00 0 0 1 1 IOPOL UiERE High-order bits of data bus SMD2 to SMD0 Figure 16.1 UARTi Block Diagram |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
