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M32C83T Datasheet(PDF) 197 Page - Renesas Technology Corp

Part # M32C83T
Description  16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  527 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C83T Datasheet(HTML) 197 Page - Renesas Technology Corp

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Page 174
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16. Serial I/O
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UARTi Transmit Buffer Register (i=0 to 4)(1)
Symbol
Address
After Reset
U0TB to U2TB 036B16-036A16, 02EB16-02EA16, 033B16-033A16
Indeterminate
U3TB, U4TB
032B16-032A16, 02FB16-02FA16
Indeterminate
RW
Transmit data (D7 to D0)
Nothing is assigned.
When write, set to "0".
When read, its content is indeterminate.
Transmit data (D8)
NOTES:
1. Use the MOV instruction to set the UiTB register.
WO
WO
(b15 - b9)
(b7 - b0)
(b8)
Function
b7
b0
b15
b8
Bit
Symbol
UARTi Receive Buffer Register (i=0 to 4)
Bit Name
Bit
Symbol
Symbol
Address
After Reset
U0RB to U2RB 036F16 - 036E16, 02EF16 - 02EE16, 033F16 - 033E16
Indeterminate
U3RB, U4RB
032F16 - 032E16, 02FF16 - 02FE16
Indeterminate
RW
Received data (D7 to D0)
ABT
(b10 - b9)
(b7 - b0)
(b8)
OER
FER
SUM
PER
Function
Overrun Error Flag(2)
Arbitration Lost
Detect Flag(1)
Framing Error
Flag(2, 3)
Parity Error Flag(2, 3)
Error Sum Flag(2, 3)
Received data (D8)
0: Not detected (win)
1: Detected (lose)
0: No overrun error occurs
1: Overrun error occurs
0: No framing error occurs
1: Framing error occurs
0: No parity error occurs
1: Parity error occurs
0: No error occurs
1: Error occurs
RW
RO
RO
RO
RO
RO
RO
NOTES:
1. The ABT bit can be set to "0" only.
2. When the SMD2 to SMD0 bits in the UiMR register is set to "0002" (serial I/O disable) or the RE bit
in the UiC1 register is set to "0" (receive disable), the OER, FER, PER and SUM bits are set to "0"
(no error occurs).
When all OER, FER and PER bits are set to "0" (no error), the SUM bit is set to "0" (no error).
Also, the FER and PER bits are set to "0" by reading low-order bits in the UiRB register.
3. These error flags are disabled when the SMD2 to SMD0 bits in the UiMR register are set to "0012"
(clock synchronous serial I/O mode, special mode 2, or special mode 3) or to "0102" (I2C mode).
When read, the contents are indeterminate.
b7
b0
b15
b8
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Figure 16.2 U0TB to U4TB Registers and U0RB to U4RB Registers



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