M32C83T datasheet(228/527 Pages) RENESAS

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Page 205

16. Serial I/O (Special Function)

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Table 16.20. Registers To Be Used and Settings in Special Mode 2

Bit

Function

UiTB

0 to 7

Set transmit data

UiRB

0 to 7

Received data can be read

OER

Overrun error flag

UiBRG

0 to 7

Set bit rate

UiMR

SMD2 to SMD0

Set to "0012"

CKDIR

Set to "0" in master mode or "1" in slave mode

IOPOL

Set to "0"

UiC0

CLK0, CLK1

Select count source for the UiBRG register

CRS

Disabled since CRD = 1

TXEPT

Transfer register empty flag

CRD

Set to "1"

NCH

Select the output format of the TxDi pin

CKPOL

Clock phase can be set by the combination of the CKPOL bit and the CKPH bit in

the UiSMR3 register

UFORM

Select either LSB first or MSB first

UiC1

Set to "1" to enable data transmission and reception

Transfer buffer empty flag

Set to "1" to enable data reception

Reception complete flag

UiIRS

Select how the UARTi transmit interrupt is generated

UiRRM

Set to "1" to enable continuous receive mode

UiLCH, SCLKSTPB Set to "0"

UiSMR

0 to 7

Set to "0016"

UiSMR2

0 to 7

Set to "0016"

UiSMR3

SSE

Set to "1"

CKPH

Clock phase can be set by the combination of the CKPH bit and the CKPOL bit

in the UiC0 register

DINC

Set to "0" in master mode or "1" in slave mode

NODC

Set to "0"

ERR

Fault error flag

5 to 7

Set to "0002"

UiSMR4

0 to 7

Set to "0016"

IFSR

IFSR6, IFSR7

Select how fault error occurs

i=0 to 4

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