M32C83T datasheet(230/527 Pages) RENESAS

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Page 207

16. Serial I/O (Special Function)

)

(

P13

P12

Microcomputer

P93(SS3)

P92(TxD3)

P90(CLK3)

P91(RxD3)

P93(SS3)

P92(SRxD3)

P90(CLK3)

P91(STxD3)

P93(SS3)

P92(SRxD3)

P90(CLK3)

P91(STxD3)

Master

Slave

Microcomputer

______

16.4.1 SSi Input Pin Function (i=0 to 4)

____

______

When the SSE bit in the UiSMR3 register is set to "1" (SS function enabled), the SSi input pin function is

selected, activating the pin function.

The DINC bit in the UiSMR3 register determines which microcomputer performs as master or slave.

______

When multiple microcomputers perform as the masters (multi-master system), the SSi pin setting deter-

mines which master microcomputer is active and when.

16.4.1.1 When Setting the DINC Bit to "1" (Slave Mode)

_____

When an "H" signal is applied to the SSi pin, the STxDi and SRxDi pins are placed in a high-imped-

ance state and the transfer clock input to the CLKi pin is ignored. When a low-level signal ("L") is

_____

applied to the SSi input pin, the transfer clock input is valid and serial communication is enabled.

16.4.1.2 When Setting the DINC Bit to "0" (Master Mode)

_____

When an "H" signal is applied to the SSi pin, serial communication is available due to transmission

_____

privilege. The master outputs the transfer clock. When an "L" signal is applied to the SSi pin, it indi-

cates that another master is active and TxDi, RxDi and CLKi pins are placed in a high-impedance

state. Moreover, a fault error occurs and the IR bit in the BCNiIC register is set to "1" (interrupt

requested). The ERR bit in the UiSMR3 register indicates whether a fault error occurs.

In master mode, software interrupt numbers 39, 40 and 41 are used for the fault error interrupt. The

fault error interrupt is generated when the ERR bit changes "0" to "1". The fault error interrupt of

UART0 and of UART3 share an interrupt vector. The fault error interrupt of UART1 and of UART4

share an interrupt vector. The IFSR6 and IFSR7 bits in the IFSR register determine which fault error

interrupt is used.

Communication is not terminated even if a fault error is generated while communicating. To stop

communication, the SMD 2 to SMD0 bit in the UiMR register is set to "0002" (serial I/O disabled).

___

Figure 16.23 Serial Bus Communication Control with SS Pin

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