M32C83T datasheet(233/527 Pages) RENESAS

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16. Serial I/O (Special Function)

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16.5 Special Mode 3 (GCI Mode)

In GCI mode, the external clock is synchronized with the transfer clock used in the clock synchronous serial

I/O mode.

Table 16.24 lists specifications of GCI mode. Table 16.25 lists registers to be used and settings. Tables

16.25 to 16.27 list pin settings.

Table16.24 GCI Mode Specifications

Item

Specification

Transfer Data Format

Transfer data : 8 bits long

Transfer Clock

The CKDIR bit in the UiMR register (i=0 to 4) is set to "1" (external clock selected):

an input from the CLKi pin

________

Clock Synchronization Function The CTSi pin inputs a trigger

Transmit/Receive Start

When a trigger signal is applied to the CTSi pin under the following conditions:

Conditions

• Set the TE bit in the UiC1 register to "1" (transmit enable)

• Set the RE bit in the UiC1 register to "1" (receive enable)

• Set the TI bit in the UiC1 register to "0" (data in UiTB register)

Interrupt Request

Transmit interrupt timing can be selected from the followings:

Generation Timing

• The UiIRS bit in the UiC1 register is set to "0" (UiTB register empty) :

when data is transferred from the UiTB register to the UARTi transmit register (transmission started)

• The UiIRS bit is set to "1" (transmit completed):

when a data transmission from the UARTi transfer register is completed

Receive interrupt timing

when data is transferred from the UARTi receive register to the UiRB register (reception completed)

Error Detection

Overrun error(1)

This error occurs when the seventh bit of the next received data is read before reading the

UiRB register.

NOTES:

1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to

"1" (interrupt requested).

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