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M32C83T Datasheet(PDF) 246 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 246 Page - Renesas Technology Corp |
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246 / 527 page  Page 223 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 16. Serial I/O (Special Function) ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M 16.7.2 Format 16.7.2.1 Direct Format Set the PRYE bit in the UiMR register (i=0 to 4) to "1", the PRY bit to "1", the UFORM bit in the UiC0 register to "0" and the UiLCH bit in the UiC1 register to "0". When data are transmitted, data set in UiTB register are transmitted with the even-numbered parity, starting from D0. When data are re- ceived, received data are stored in the UiRB register, starting from D0. The even-numbered parity determines whether a parity error occurs. 16.7.2.2 Inverse Format Set the PRYE bit to "1", the PRY bit to "0", the UFORM bit to "1" and the UiLCH bit to "1". When data are transmitted, values set in the UiTB register are logically inversed and are transmitted with the odd-numbered parity, starting from D7. When data are received, received data are logically inversed to be stored in the UiRB register, starting from D7. The odd-numbered parity determines whether a parity error occurs. D0 D1 D2 D3 D4 D5 D6 D7 P Transfer Clock TxDi TxDi D7 D6 D5 D4 D3 D2 D1 D0 P (1) Direct Format Transfer Clock (2) Inverse Format P : Odd parity "H" "L" "H" "L" "H" "L" "H" "L" P : Even parity i=0 to 4 Figure 16.32 SIM Interface Format |
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