M32C83T datasheet(248/527 Pages) RENESAS

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17. A/D Converter

)

(

Table 17.1 A/D Converter Specifications

Item

Specification

A/D Conversion Method

Successive approximation (with a capacitive coupling amplifier)

Analog Input Voltage(1)

0V to AVCC (VCC)

Operating Clock, ØAD(2)

fAD, fAD/2, fAD/3, fAD/4

Resolution

Select from 8 bits or 10 bits

Operating Mode

One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,

repeat sweep mode 1

Analog Input Pins(3)

34 pins

8 pins each for AN (AN0 to AN7), AN0 (AN00 to AN07), AN2 (AN20 to AN27),

AN15 (AN150 to AN157)

2 extended input pins (ANEX0 and ANEX1)

A/D Conversion Start Condition

Software trigger

• The ADST bit in the ADiCON0 (i=0, 1) register is set to "1" (A/D conversion

started) by program

• The PST bit in the AD0CON2 register is set to "1" (A/D0 and A/D1 start a

conversion simultaneously) by program

External trigger (re-trigger is enabled)

__________

When a falling edge is applied to the ADTRG pin after the ADST bit is set to "1" by

program

Hardware trigger (re-trigger is enabled)

One of the following interrupt requests is generated after the ADST bit is set to

"1" by program:

• The timer B2 interrupt request of the three-phase motor control timer functions

(after the ICTB2 counter completes counting)

• The intelligent I/O interrupt request

Channel 1 in the group 2 (A/D0), channel 1 in the group 3 (A/D1)

Conversion Rate Per Pin

• Without the sample and hold function

8-bit resolution : 49 ØAD cycles

10-bit resolution : 59 ØAD cycles

• With the sample and hold function

8-bit resolution : 28 ØAD cycles

10-bit resolution : 33 ØAD cycles

NOTES:

1. Analog input voltage is not affected by the sample and hold function status.

2. ØAD frequency must be under 16 MHz when VCC=5V.

ØAD frequency must be under 10 MHz when VCC=3.3V.

Without the sample and hold function, the ØAD frequency must be 250 kHz or more.

With the sample and hold function, the ØAD frequency must be 1 MHz or more.

3. AVCC = VREF = VCC, A/D input voltage (for AN0 to AN7, AN00 to AN07, AN20 to AN27, AN150 to AN157, ANEX0

and ANEX1)

≤ VCC.

Table 19.2 Difference between A/D0 and A/D1

Item

A/D0

A/D1

Analog Input Pins(1)

AN (AN0 to AN7)

Select from AN0 (AN00 to AN07),

AN2 (AN20 to AN27) or AN15 (AN150 to AN157)

Extended Analog Input Pins

ANEX0, ANEX1

Not provided

External Op-Amp(1)

Enabled

Disabled

Intelligent I/O used as a Trigger

Channel 1 in group 2

Channel 1 in group 3

NOTES:

1. When the ADS bit in the AD0CON2 register is set to "0" (channel replacement disabled)

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