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M32C83T Datasheet(PDF) 244 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 244 Page - Renesas Technology Corp |
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244 / 527 page  Page 221 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 16. Serial I/O (Special Function) ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M Figure 16.29 SIM Interface Operation D0 D1 D2 D3 D4 D5 D6 D7 ST P D0 D1 D2 D3 D4 D5 D6 D7 ST P SP D0 D1 D2 D3 D4 D5 D6 D7 ST P D0 D1 D2 D3 D4 D5 D6 D7 ST P SP D0 D1 D2 D3 D4 D5 D6 D7 ST P D0 D1 D2 D3 D4 D5 D6 D7 ST P SP SP D0 D1 D2 D3 D4 D5 D6 D7 ST P D0 D1 D2 D3 D4 D5 D6 D7 ST P SP SP Start bit Parity bit "0" "1" "0" "1" "0" "1" Set to "0" by an interrupt request acknowledgement or by program Tc Transfer Clock Stop bit Data is written to the UiTB register An "L" signal is applied from the SIM card due to a parity error An interrupt routine detects "H" or "L" TxDi "0" "1" Transfer Clock Read the UiRB register Signal Line Level(3) TxDi Signal Line Level(2) NOTES: 1. Data transmission starts when BRG overflows after a value is set to the UiTB register on the rising edge of the TI bit. 2. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the TxDi pin and parity error signal from the receiving end, is generated. 3. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the transmitting end and parity error signal from the TxDi pin, is generated. 4. The CNT3 to CNT0 bits in the TCSPR register selects no division (n=0) or divide-by-2n (n=1 to 15). Data is transferred from the UiTB register to the UARTi transmit register (Note 1) RE bit in the UiC1 register RI bit in the UiC1 register IR bit in the SiRIC register TE bit in the UiC1 register TI bit in the UiC1 register TXEPT bit in the UiC0 register IR bit in the SiTIC register i=0 to 4 The above applies under the following conditions: • The PRYE bit in the UiMR register is set to "1" (parity enabled) • The STPS bit in the UiMR register is set to "0" (1 stop bit) • The UiIRS bit in the UiC1 register is set to "1" (interrupt request generated when transmission completed) Tc = 16(m+1) / fj fj: count source frequency of the UiBRG register (f1, f8, f2n(4)) m: setting value of the UiBRG register Start bit Set to "0" by an interrupt request acknowledgement or by program Stop bit TxDi outputs "L" due to a parity error i=0 to 4 The above applies under the following conditions: • The PRYE bit in the UiMR register is set to "1" (parity enabled) • The STPS bit in the UiMR register is set to "0" (1 stop bit) Tc = 16(m+1) / fj fj: count source frequency of the UiBRG register (f1, f8, f2n(4)) m: setting value of the UiBRG register Parity bit "0" "1" "0" "0" "1" (1) Transmit Timing (2) Receive Timing Parity Error Signal returned from Receiving End Transmit Waveform from the Transmitting End "1" SP An interrupt routine detects "H" or "L" SP |
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