M32C83T datasheet(241/527 Pages) RENESAS

241 / 527 page

Page 218

16. Serial I/O (Special Function)

)

(

16.7 Special Mode 5 (SIM Mode)

In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are

available and the TxDi pin (i=0 to 4) can output an "L" signal when a parity error is detected.

Table 16.34 lists specifications of SIM mode. Table 16.35 lists registers to be used and register settings in

SIM mode. Tables 16.36 to 16.38 list the pin settings.

Table16.34 SIM Mode Specifications

Item

Specification

Transfer Data Format

• Transfer data: 8-bit UART mode

• One stop bit

• In direct format

Parity:

Even

Data logic:

Direct

Transfer format: LSB first

• In inverse format

Parity:

Odd

Data logic:

Inverse

Transfer format: MSB first

Transfer Clock

The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected):

fj/16(m+1)(1) fj = f1, f8, f2n(2) m : setting value of the UiBRG register

0016 to FF16

Do not set the CKDIR bit to "1" (external clock selected)

Transmit/Receive Control The CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled)

Other Setting Items

The UiIRS bit in the UiC1 register is set to "1" (transmission completed)

Transmit Start Condition To start transmitting, the following requirements must be met:

• Set the TE bit in the UiC1 register to "1" (transmit enable)

• Set the TI bit in the UiC1 register to "0" (data being in the UiTB register)

Receive Start Condition To start receiving, the following requirements must be met:

• Set the RE bit in the UiC1 register to "1" (receive enable)

• Detect the start bit

Interrupt Request

Transmit interrupt timing

Generation Timing

• The UiIRS bit is set to "1" (transmission is completed):

when data transmission from the UARTi transfer register is completed

Receive interrupt timing

when data is transferred from the UARTi receive register to the UiRB register (reception completed)

Error Detection

• Overrun error(1)

This error occurs when the eighth bit of the next data is received before reading the UiRB register

• Framing error

This error occurs when the number of the stop bit set is not detected

• Parity error

This error occurs when the number of "1" in parity bit and character bits differ from

the number set.

• Error sum flag

The SUM bit is set to "1" when an overrun error, framing error or parity error occurs.

NOTES:

1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to

"1" (interrupt requested).

2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

M32C83T Datasheet(PDF) 241 Page - Renesas Technology Corp

M32C83T Datasheet(HTML) 241 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL