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M32C83T Datasheet(PDF) 310 Page - Renesas Technology Corp

Part # M32C83T
Description  16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  527 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C83T Datasheet(HTML) 310 Page - Renesas Technology Corp

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21. Intelligent I/O (Waveform Generation Function)
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21.3.6 Parallel Real-Time Port Output Mode (Group 2 and 3)
The OUTCij pin outputs the value set by the GiRTP register in one-byte units when the value of the base
timer matches that of the GiPOj register (i=2 to 3, j=0 to 7). Table 21.15 lists specifications of the parallel
RTP output mode. Figure 21.30 shows a block diagram of the parallel RTP output function. Figure 21.31
shows an example of the parallel RTP output mode operation. (See Figure 21.7 for the G2BCR1 register
and Figure 21.8 for the G3BCR1 register.)
Table 21.15 Parallel RTP Output Mode Specifications
Item
Specification
Waveform Output Start Condition
The IFEj bit in the GiFE register (i=2 to 3, j=0 to 7) is set to "1" (channel j function
enabled)
Waveform Output Stop Condition
The IFEj bit is set to "0" (channel j function disabled)
Interrupt Request
The POijR bit in the interrupt request register is set to "1" when value of the
base timer matches that of the GiPOj register (000016 to FFFF16(1)). (See
Figure 10.14.)
OUTCij Pin
RTP output
Selectable Function
• Default value set function: Set starting waveform output level
• Inverse output function: Waveform output level is inversed and output from
the OUTCij pin
NOTES:
1. Set the GiPO0 register to 000116 to FFFD16 when setting the base timer to "000016" (the RST1 bit in the GiBCR1
register is set to "1", and the RST0 and RST2 bits are set to "0") while the values in the base timer and the GiPO0
register match
DQ
T
RTP0
RTP1
RTP2
RTP3
RTP4
RTP5
RTP6
RTP7
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
DQ
T
Real-time Port Output
GiRTP register
GiPO0 register
Base Timer
GiPO1 register
GiPO2 register
GiPO3 register
GiPO4 register
GiPO5 register
GiPO6 register
GiPO7 register
OUTCi0
OUTCi1
OUTCi2
OUTCi3
OUTCi4
OUTCi5
OUTCi6
OUTCi7
i=2 to 3
Figure 21.30 Parallel RTP Output Function Block Diagram



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