M32C83T datasheet(306/527 Pages) RENESAS

306 / 527 page

Page 283

21. Intelligent I/O (Waveform Generation Function)

)

(

fBTi

21.3.4 Bit Modulation PWM Output Mode (Group 2 and 3)

In bit modulation PWM output mode, PWM output has a 16-bit resolution. Pulses are output in repetitive

cycles, each cycle consisting of span t repeated 1024 times. Span t, itself, has a cycle of

. The six

high-order bits in the GiPOj register (i=2 to 3; j=0 to 7) determine the "L" base width. The 10 low-order bits

determine the number of span t, within a cycle, in which "L" width is extended by the minimum resolution bit

width (1 clock cycle). If the INV bit is set to "1" (output is inversed), the level of the waveform being output

is inversed.

Table 21.12 lists specifications of bit modulation PWM output mode. Table 21.13 lists the number of

modulated span and minimum resolution bit width altered span t. Figure 21.27 shows an example of bit

modulation PWM mode operation.

Table 21.12 Bit Modulation PWM Output Mode Specifications

Item

Specification

Output Waveform(1,2)

PWM-repeated cycle T:

X1024)

Cycle of span t:

"L" width: of m spans

of (1024-m) spans

Average "L" output width:

X (n+

)

n: Setting values (six high-order bits) of the GiPOj register (i=2 to 3; j=0 to 7)

0016 to 3F16

m: Setting values (ten low-order bits) of the GiPOj register 0016 to 3FF16

Waveform Output Start Condition

The IFEj bit in the GiFE register is set to "1" (channel j function enabled)

Waveform Output Stop Condition

The IFEj bit is set to "0" (channel j function disabled)

Interrupt Request

The POijR bit in the interrupt request register is set to "1" when the value of the

six low-order bits of the base timer matches those set in the six high-order bits

of the GiPOj register (see Figure 10.14).

OUTCij Pin

Pulse signal output pin

Selectable Function

• Default value set function : Set starting waveform output level

• Inversed output function : Waveform output level is inversed and output from

the OUTCij pin

NOTES:

1. Set the RST2 to RST0 bits in the GiBCR1 register to "0002" when using the bit modulation PWM mode.

2. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed.

Table 21.13. Number of Modulated Spans and Minimum Resolution Bit Width Extended Span t

Number of Modulated Spans

Minimum Resolution Bit Width Extended Span t

00 0000 00002

none

00 0000 00012

t512

00 0000 00102

t256, t768

00 0000 01002

t128, t384, t640, t896

00 0000 10002

t64, t192, t320, t448, t576, t704, t832, t960

10 0000 00002

t1, t3, t5, t7,

t1019, t1021, t1023

fBTi

n+1

fBTi

1024

65536

fBTi

•••

M32C83T Datasheet(PDF) 306 Page - Renesas Technology Corp

M32C83T Datasheet(HTML) 306 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL