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M32C83T Datasheet(PDF) 303 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 303 Page - Renesas Technology Corp |
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303 / 527 page ![]() Page 280 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 21. Intelligent I/O (Waveform Generation Function) ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M 21.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode (Group 0 to 3) Output signal level of the OUTCij pin (i=0 to 3; j=0, 2, 4, 6) becomes "H" when the value of the base timer matches that of the GiPOj register. The "H" signal switches to an "L" signal when the value of the base timer matches that of the GiPOk register (k=j+1) or when the base timer is set to "000016". If the IVL bit in the GiPOCRj register (j=0 to 7) is set to "1" (outputs "H" as initial value), an "H" signal is output when waveform output starts. If the INV bit is set to "1" (output is inversed), the level of the waveform being output is inversed. Table 21.11 lists specifications of SR waveform mode. Figure 21.26 shows an ex- ample of a SR waveform mode operation. Table 21.11 SR Waveform Output Mode Specifications (1/2) Item Specification Output Waveform(2) • Free-running operation (the RST2 to RST0 bits in the GiBCR1 register are set to "0002") (1) m < n "H" width : "L" width : (2) m ≥ n "H" width : "L" width : m : setting value of the GiPOj register (j=0, 2, 4, 6) n : setting value of the GiPOk register (k=j+1) m, n=000016 to FFFF16 • The base timer is reset by matching the base timer with the GiPO0 register(1) (the RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0") (1) m < n < p+2 "H" width : "L" width : (2) m < p+2 ≤ n "H" width : "L" width : (3) If m ≥ p+2, the output level is fixed to "L" m : setting value of the GiPOj register (j=2, 4, 6) n : setting value of the GiPOk register (k=j+1) p : setting value of the GiPO0 register m, n=000016 to FFFF16 p=000116 to FFFD16 NOTES: 1. When the GiPO0 register resets the base timer, the channel 0 and 1 SR waveform generation functions are not available. 2. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed. 3. Waveform from base timer reset until when output level becomes "H". 4. Waveform from when output level becomes "L" until base timer reset. m (3) fBTi n - m fBTi + 65536 - n(4) fBTi 65536 - m fBTi m fBTi n-m fBTi m (3) fBTi + p + 2 - n(4) fBTi p + 2 - n fBTi m fBTi |
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