| Electronic Components Datasheet Search |
|
M32C83T Datasheet(PDF) 299 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
M32C83T Datasheet(HTML) 299 Page - Renesas Technology Corp |
|
299 / 527 page ![]() Page 276 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 21. Intelligent I/O (Waveform Generation Function) ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M m fBTi 65536-m fBTi n+2 fBTi m fBTi n+2-m fBTi 65536 fBTi 21.3.1 Single-Phase Waveform Output Mode (Group 0 to 3) Output signal level of the OUTCij pin (i=0 to 3; j=0 to 7) becomes high ("H") when the value of the base timer matches that of the GiPOj register . The "H" signal switches to an "L" signal when the base timer reaches "000016". If the IVL bit in the GiPOCRj register is set to "1" (outputs "H" as default value), an "H" signal is output when waveform output starts. If the INV bit is set to "1" (output inversed), the level of the waveform being output is inversed. See Figure 21.24 for details on single-phase waveform mode opera- tion. Table 21.9 lists specifications of single-phase waveform mode. Table 21.9 Single-phase Waveform Output Mode Specifications Item Specification Output Waveform(3) • Free-running operation (the RST2 to RST0 bits in the GiBCR1 (i=0 to 3) register are set to "0002") Cycle : "L" width : "H" width : m : setting value of the GiPOj register (j=0 to 7), 000016 to FFFF16 • The base timer is reset by matching the base timer with the GiPO0 register (the RST1 bit is set to "1", and the RST0 and the RST2 bit are set to "0") Cycle : "L" width : "H" width : m : setting value of the GiPOj register (j=1 to 7), 000016 to FFFF16 n : setting value of the GiPO0 register, 000116 to FFFD16 If m ≥ n+2, the output level is fixed to "L" Waveform Output Start Condition(1) The IFEj bit in the GiFE register is set to "1" (channel j function enabled) Waveform Output Stop Condition The IFEj bit is set to "0" (channel j function disabled) Interrupt Request The POijR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the GiPOj register. (See Figure 10.14) OUTCij Pin(2) Pulse signal output pin Selectable Function • Default value set function : Set starting waveform output level • Inversed output function : Waveform output level is inversed and output from the OUTCij pin • Cascaded connection function: Connect group 0 and group 1 to operate as a 32-bit base timer NOTES: 1. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by both time measurement function and waveform generation function 2. OUTC00, OUTC01, OUTC04, OUTC05, OUTC10 to OUTC17, OUTC20 to OUTC27, and OUTC30 to OUTC37 pins (OUTC10 to OUTC17 pins when using group 0 and group 1 cascaded connection) 3. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |