M32C83T datasheet(298/527 Pages) RENESAS

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Page 275

21. Intelligent I/O (Waveform Generation Function)

)

(

Table 21.7 Pin Settings for Waveform Generation Function (2/2)

Bit and Setting

PS0 to PS2, PS5 to PS9 Registers

PSL0, PSL1, PSL2, PSL3 Registers

PSC Register

P132/OUTC26(1)

PS7_2 = 1

P133/OUTC23(1)

PS7_3 = 1

P134/OUTC20(1)

PS7_4 = 1

P135/OUTC22(1)

PS7_5 = 1

P136/OUTC21(1)

PS7_6 = 1

P137/OUTC27(1)

PS7_7 = 1

P140/OUTC14(1,2)

PS8_0 = 1

P141/OUTC15(1,2)

PS8_1 = 1

P142/OUTC16(1,2)

PS8_2 = 1

P143/OUTC17(1,2)

PS8_3 = 1

P150/OUTC00(1,2)

PS9_0 = 1

P151/OUTC01(1,2)

PS9_1 = 1

P154/OUTC04(1,2)

PS9_4 = 1

P155/OUTC05(1,2)

PS9_5= 1

NOTES:

1. This port is provided in the 144-pin package only.

2. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement function), the OUTC1j pin (j=0 to 7)

outputs a waveform and the OUTC0k pin (k=0, 1, 4, 5), set as above, outputs a 16-bit low-order waveform.

Table 21.8 Waveform Generation Function Associated Register Settings

Bit

Function

GiPOCRj

MOD2 to MOD0

Select waveform output mode

PRT(1)

Set to "1" when using the parallel RTP output mode

IVL

Select default value

RLD

Select reload timing of GiPOj register value

RTP(1)

Set to "1" when using the RTP output or the parallel RTP output mode

MOD2 to MOD0 bits are invalid when the RTP bit is set to "1"

INV

Select inversed output

G2BCR1

PRP

Set to "1" when using the parallel RTP output mode

G3BCR1

GiPOj

Select output waveform inverse timing

G3MK4 to

Set masked values of the base timer and G3PO4 to G3PO7 registers

G3MK7

(group 3 only)

GiFS

FSCj

Set to "0" (waveform generation function) (group 0 and 1 only)

GiFE

IFEj

Set to "1" (enables channel j function)

G2RTP

RTP0 to

Set RTP output value in RTP output or parallel RTP output mode

G3RTP

RTP7

i = 0 to 3; j = 0 to 7

Bit configurations and functions vary with channels and groups used.

Set registers associated with the waveform generation function after setting registers associated with the base timer.

NOTES:

1. This bit is in the G2POCRj and G3POCRj registers only.

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