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M32C83T Datasheet(PDF) 304 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 304 Page - Renesas Technology Corp |
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304 / 527 page ![]() Page 281 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 21. Intelligent I/O (Waveform Generation Function) ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M Table 21.11 SR Waveform Output Mode Specifications (2/2) Item Specification Waveform Output Start Condition(5) The IFEq bit (q=0 to 7) in the GiFE register is set to "1" (channel q function enabled) Waveform Output Stop Condition The IFEq bit is set to "0" (channel q function disabled) Interrupt Request The POijR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the GiPOj register. The POikR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the GiPOk register. (See Figure 10.14) OUTCij Pin(6) Pulse signal output pin Selectable Function • Default value set function : Set starting waveform output level • Inversed output function : Waveform output level is inversed and output from the OUTCij pin • Cascaded connection function: Connect group 0 and group 1 to operate as a 32-bit base timer NOTES: 5. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by both time measurement function and waveform generation function 6. OUTC00, OUTC04, OUTC10, OUTC12, OUTC14, OUTC16, OUTC20, OUTC22, OUTC24, OUTC26, OUTC30, OUTC32, OUTC34, and OUTC36 pins (OUTC10, OUTC12, OUTC14, and OUTC16 pins when using group 0 and group 1 cascaded connection) |
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