M32C87 datasheet(13/627 Pages) RENESAS

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23.1.18

CANi Single-Shot Status Register (CiSSSTR Register) (i = 0, 1) ................................................... 430

23.1.19

CANi Global Mask Register, CANi Local Mask Register A, and CANi Local Mask Register B

(CiGMRk, CiLMARk, and CiLMBRk Registers) (i = 0,1, k = 0 to 4) ............................................ 432

23.1.20

CANi Message Slot j Control Register (CiMCTLj Register) (i = 0, 1, j = 0 to 15) ......................... 438

23.1.21

CANi Slot Buffer Select Register (CiSBS Register) (i = 0, 1) ......................................................... 442

23.1.22

CANi Message Slot Buffer j (i = 0, 1; j = 0, 1) ................................................................................ 443

23.1.23

CANi Acceptance Filter Support Register (CiAFS Register) (i = 0, 1) ........................................... 447

23.2

CAN Clock and CPU Clock .................................................................................................................. 448

23.2.1

CAN Clock ....................................................................................................................................... 448

23.2.2

CPU Clock ........................................................................................................................................ 448

23.3

Setting and Timing in CAN-Associated Registers ................................................................................ 449

23.3.1

CAN Module Initialize Timing ........................................................................................................ 449

23.3.2

CAN Transmit Timing ...................................................................................................................... 450

23.3.3

CAN Receive Timing ....................................................................................................................... 451

23.3.4

CAN Bus Error Timing .................................................................................................................... 452

23.4

CAN Interrupts ...................................................................................................................................... 453

23.4.1

CAN1 Wake-Up Interrupt ................................................................................................................ 454

23.4.2

CANij Interrupt ................................................................................................................................. 454

24.

Real-Time Port (RTP) ................................................................................................................. 458

25.

Programmable I/O Ports ............................................................................................................. 461

25.1

Port Pi Direction Register (PDi Register, i = 0 to 15) ........................................................................... 461

25.2

Port Pi Register (Pi Register, i = 0 to 15) .............................................................................................. 461

25.3

Function Select Register A (PSj Register, j = 0 to 9) ............................................................................ 461

25.4

Function Select Register B (PSLk Register, k = 0 to 3, 5 to 7, 9) ........................................................ 461

25.5

Function Select Register C (PSC, PSC2, PSC3, and PSC6 Registers) ................................................. 461

25.6

Function Select Register D (PSD1 and PSD2 Registers) ...................................................................... 462

25.7

Function Select Register E (PSE1 and PSE2 Registers) ....................................................................... 462

25.8

Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers) ................................................................. 462

25.9

Port Control Register (PCR Register) ................................................................................................... 462

25.10

Input Function Select Register (IPS, IPSA, and IPSB Registers) ......................................................... 462

25.11

Analog Input and Other Peripheral Function Input ............................................................................... 462

26.

Flash Memory ............................................................................................................................. 493

26.1

Memory Map ......................................................................................................................................... 494

26.1.1

Boot Mode ........................................................................................................................................ 495

26.2

Functions to Prevent Access to Flash Memory ..................................................................................... 495

26.2.1

ROM Code Protect Function ............................................................................................................ 495

26.2.2

ID Code Check Function .................................................................................................................. 495

26.3

CPU Rewrite Mode ............................................................................................................................... 497

26.3.1

Flash Memory Control Register (FMR0 and FMR1 Registers) ....................................................... 498

26.3.2

Software Commands ......................................................................................................................... 504

26.3.3

Data Protect Function ....................................................................................................................... 509

26.3.4

Status Register (SRD Register) ........................................................................................................ 509

26.3.5

Full Status Check .............................................................................................................................. 510

26.4

Standard Serial I/O Mode ...................................................................................................................... 512

26.4.1

Pin Handling in Standard Serial I/O Mode ....................................................................................... 517

26.5

Parallel I/O Mode .................................................................................................................................. 518

26.5.1

Boot ROM Area ................................................................................................................................ 518

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