HD64F36054 datasheet(71/592 Pages) RENESAS

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Section 2 CPU

Rev. 4.00 Mar. 15, 2006 Page 39 of 556

REJ09B0026-0400

2.6.2

On-Chip Peripheral Modules

On-chip peripheral modules are accessed in two states, three states, or four states. The data bus

width is 8 bits or 16 bits depending on the register. For description on the data bus width and

number of accessing states of each register, refer to section 21.1, Register Addresses (Address

Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-

bit data bus width can be accessed by byte or word size. When a register with 8-bit data bus width

is accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the

same as that for on-chip memory. Figure 2.10 shows the operation timing in the case of three-state

access to an on-chip peripheral module. In four-state access, the operation timing is such that a

wait cycle is inserted between the T

2 and T3 states.

T1 state

Bus cycle

Internal

address bus

Internal

read signal

Internal

data bus

(read access)

Internal

write signal

Read data

Address

Internal

data bus

(write access)

T2 state

T3 state

Write data

SUB

φ or φ

Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)

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