HD64F36054 datasheet(15/592 Pages) RENESAS

15 / 592 page

Rev. 4.00 Mar. 15, 2006 Page xv of xxxii

14.5.1

Clock................................................................................................................. 278

14.5.2

SCI3 Initialization............................................................................................. 278

14.5.3

Serial Data Transmission .................................................................................. 279

14.5.4

Serial Data Reception (Clocked Synchronous Mode)....................................... 281

14.5.5

Simultaneous Serial Data Transmission and Reception.................................... 283

14.6

Multiprocessor Communication Function......................................................................... 285

14.6.1

Multiprocessor Serial Data Transmission ......................................................... 286

14.6.2

Multiprocessor Serial Data Reception .............................................................. 287

14.7

Interrupts........................................................................................................................... 291

14.8

Usage Notes ...................................................................................................................... 292

14.8.1

Break Detection and Processing ....................................................................... 292

14.8.2

Mark State and Break Sending.......................................................................... 292

14.8.3

Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only).................................................................. 292

14.8.4

Receive Data Sampling Timing and Reception Margin in Asynchronous

Mode ................................................................................................................. 293

Section 15 Controller Area Network for Tiny (TinyCAN) ...............................295

15.1

Features............................................................................................................................. 295

15.2

Input/Output Pins .............................................................................................................. 297

15.3

Register Descriptions ........................................................................................................ 297

15.3.1

Test Control Register (TCR)............................................................................. 298

15.3.2

Master Control Register (MCR) ....................................................................... 300

15.3.3

TinyCAN Module Control Register (TCMR)................................................... 301

15.3.4

General Status Register (GSR) ......................................................................... 302

15.3.5

Bit Configuration Registers 0, 1 (BCR0, BCR1) .............................................. 304

15.3.6

Mailbox Configuration Register (MBCR) ........................................................ 306

15.3.7

Transmit Pending Register (TXPR) .................................................................. 307

15.3.8

Transmit Pending Cancel Register (TXCR) ..................................................... 308

15.3.9

Transmit Acknowledge Register (TXACK) ..................................................... 308

15.3.10

Abort Acknowledge Register (ABACK) .......................................................... 309

15.3.11

Data Frame Receive Complete Register (RXPR) ............................................. 310

15.3.12

Remote Request Register (RFPR)..................................................................... 310

15.3.13

Unread Message Status Register (UMSR)........................................................ 311

15.3.14

TinyCAN Interrupt Registers 0, 1 (TCIRR0, TCIRR1).................................... 312

15.3.15

Mailbox Interrupt Mask Register (MBIMR)..................................................... 315

15.3.16

TinyCAN Interrupt Mask Registers 0, 1 (TCIMR0, TCIMR1) ........................ 315

15.3.17

Transmit Error Counter (TEC).......................................................................... 318

15.3.18

Receive Error Counter (REC) ........................................................................... 318

15.4

Message Data and Control ................................................................................................ 319

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