HD64F2633 datasheet(29/1487 Pages) RENESAS

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Rev. 5.00 Mar 28, 2005 page xxix of lxii

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11.2.1 Timer

Control Register

(TCR)

534

Bits 4 and 3

Clock Edge 1 and 0 (CKEG1, CKEG0)

Note of bit table amended

Note: Internal clock edge selection is valid when the input clock is

φ/4 or slower. This setting is ignored if the input clock is φ/1, or

when overflow/underflow of another channel is selected. (The

clock is counted at the falling edge when

φ/1 is selected.)

11.7 Usage Notes

Figure 11.57

Contention

between TCNT

Write and Overflow

615

Figure amended

TCNT

H'FFFF

TCFV flag

Prohibited

15.1.2 Block

Diagram

Figure 15.1 (a)

Block Diagram of

WDT0

684

Note *2 added

Overflow

Interrupt

control

WOVI 0

(interrupt request

signal)

WDTOVF

Internal reset signal*1

Reset

control

φ/2*2

φ/64*2

φ/128*2

φ/512*2

φ/2048*2

φ/8192*2

φ/32768*2

φ/131072*2

Clock

select

Internal clock

sources

Notes: 1. The type of internal reset signal depends on a register

setting.

2. The

φ in the subactive and subsleep mode is φSUB.

15.2.2 Timer

Control/Status

691

WDT0 Input Clock Select

Note *2 added

Clock*

2 Overflow Period*1

Notes: 1. An overflow period is the time interval ...

2. The

φ in the subactive and subsleep mode is φSUB.

16.3.2 Operation

in Asynchronous

Mode

Figure 16.7

Sample Serial

Reception Data

Format

746

Note * added

DMAC* DTC*

Note: * The DMAC and DTC are not available in the H8S/2695.

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