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HD64F36022G Datasheet(PDF) 97 Page - Renesas Technology Corp |
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HD64F36022G Datasheet(HTML) 97 Page - Renesas Technology Corp |
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97 / 384 page ![]() Section 6 Power-Down Modes Rev. 4.00 Sep. 23, 2005 Page 71 of 354 REJ09B0025-0400 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value R/W Description 7 SMSEL 0 R/W Sleep Mode Selection This bit selects the mode to transit after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2. 6 0 Reserved This bit is always read as 0. 5 DTON 0 R/W Direct Transfer on Flag This bit selects the mode to transit after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2. 4 3 2 MA2 MA1 MA0 0 0 0 R/W R/W R/W Active Mode Clock Select 2 to 0 These bits select the operating clock frequency in active and sleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 0XX: φ OSC 100: φ OSC/8 101: φ OSC/16 110: φ OSC/32 111: φ OSC/64 1, 0 All 0 Reserved These bits are always read as 0. Legend: X : Don't care. |
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