ADS62P22 datasheet(13/71 Pages) TI

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SERIAL INTERFACE

SERIAL INTERFACE TIMING CHARACTERISTICS

ADS62P25, ADS62P24

ADS62P23, ADS62P22

SLAS576A – OCTOBER 2007 – REVISED FEBRUARY 2008

The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN

(Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).

Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge

of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge

when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be

loaded in multiple of 16-bit words within a single active SEN pulse.

The first 8 bits form the register address and the remaining 8 bits the register data. The interface can work with

SCLK frequency from 20 MHz down to low speeds (few Hertz), and also with a non-50% SCLK duty cycle.

After power-up, the internal registers must be initialized to their default values. This can be done in one of two

ways:

1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as

shown in Figure 5.

2. By applying software reset. Using the serial interface, set the <RST> bit to high. This initializes internal

registers to their default values and then self-resets the <RST> bit to low. In this case the RESET pin is kept

low.

Typical values at 25

°C, min and max values across the full temperature range T

MIN = –40°C to TMAX = 85°C, AVDD = 3.3 V,

DRVDD = 1.8 V to 3.3 V, unless otherwise noted.

PARAMETER

MIN

TYP

MAX

UNIT

fSCLK

SCLK frequency

> DC

MHz

tSLOADS

SEN to SCLK setup time

tSLOADH

SCLK to SEN hold time

tDSU

SDATA setup time

tDH

SDATA hold time

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Product Folder Link(s): ADS62P25, ADS62P24 ADS62P23, ADS62P22

ADS62P22 Datasheet(PDF) 13 Page - Texas Instruments

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