M32CSLASH8A datasheet(82/372 Pages) RENESAS

Part #	M32C/8A

Description	RENESAS MCU M16C FAMILY / M32C/80 Series

PDF	372 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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M32C/8A Group

8. Bus

Rev.1.00

Jul 15, 2007

Page 65 of 352

REJ09B0385-0100

8.2.8

External Bus States when Accessing Internal Space

Table 8.9 lists external bus states when the internal space is accessed.

Table 8.9

External Bus States when Accessing Internal Space

8.2.9

BCLK Output

The bus clock can be output from the BCLK pin in microprocessor mode. To output the bus clock, set the

PM07 bit in the PM0 register to 0 (BCLK output) and bits CM01 and CM00 in the CM0 register to 00b (I/O

port P5_3).

Refer to 9. Clock Generation Circuits for details.

Item

State when Accessing SFR and Internal RAM

A0 to A22, A23

Hold the last accessed address in the external space

D0 to D15

High-impedance

RD, WR, WRL, WRH

Outputs “H”

BHE

Holds the output level at the time when the MCU accessed the external

space or SFR area for the last time

Outputs “H”

ALE

Outputs ALE signal

M32C/8A Datasheet(PDF) 82 Page - Renesas Technology Corp