M32CSLASH8A datasheet(90/372 Pages) RENESAS

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M32C/8A Group

9. Clock Generation Circuits

Rev.1.00

Jul 15, 2007

Page 73 of 352

REJ09B0385-0100

Figure 9.4

MCD Register

b7 b6 b5 b4

Main Clock Division Register(1)

Symbol

MCD

Address

000Ch

Bit Symbol

Bit Name

MCD0

After Reset

XXX0 1000b

NOTES:

1. Set the MCD register after the PRC0 bit in the PRCR register is set to 1 (write enable).

2. When stop mode or low-power consumption mode is entered, bits MCD4 to MCD0 become 01000b.

In on-chip oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit in the CM0 register is set to 1 (main

clock stops).

Function

Main clock division

select bits(2)

MCD1

MCD2

b4 b3 b2 b1 b0

1 0 0 1 0: Divide-by-1 (no division) mode

0 0 0 1 0: Divide-by-2 mode

0 0 0 1 1: Divide-by-3 mode

0 0 1 0 0: Divide-by-4 mode

0 0 1 1 0: Divide-by-6 mode

0 1 0 0 0: Divide-by-8 mode

0 1 0 1 0: Divide-by-10 mode

0 1 1 0 0: Divide-by-12 mode

0 1 1 1 0: Divide-by-14 mode

0 0 0 0 0: Divide-by-16 mode

Do not set to values other than the above

MCD3

MCD4

−

(b7-b5)

−

Reserved bits

Read as undefined value

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