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HD6432142 Datasheet(PDF) 775 Page - Renesas Technology Corp |
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HD6432142 Datasheet(HTML) 775 Page - Renesas Technology Corp |
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775 / 1177 page ![]() Section 24 Clock Pulse Generator Rev. 4.00 Sep 27, 2006 page 731 of 1130 REJ09B0327-0400 Section 24 Clock Pulse Generator 24.1 Overview This LSI have a built-in clock pulse generator (CPG) that generates the system clock ( φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock input circuit, and waveform shaping circuit. 24.1.1 Block Diagram Figure 24.1 shows a block diagram of the clock pulse generator. EXTAL XTAL Oscillator Duty adjustment circuit EXCL Subclock input circuit Waveform shaping circuit Medium-speed clock divider System clock To φ pin WDT1 count clock Internal clock To supporting modules Bus master clock To CPU, DTC φ/2 to φ/32 φ SUB φ Bus master clock selection circuit Clock selection circuit Figure 24.1 Block Diagram of Clock Pulse Generator |
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