HD6432142 datasheet(863/1177 Pages) RENESAS

863 / 1177 page

Section 26 Electrical Characteristics

Rev. 4.00 Sep 27, 2006 page 819 of 1130

REJ09B0327-0400

(1) Clock Timing

Table 26.20 shows the clock timing. The clock timing specified here covers clock (

φ) output and

clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times.

For details of external clock input (EXTAL pin and EXCL pin) timing, see section 24, Clock

Pulse Generator.

Table 26.20 Clock Timing

Condition A: V

CC = 5.0 V ±10%, VCCB = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum

operating frequency, T

a = –20 to +75°C (regular specifications),

a = –40 to +85°C (wide-range specifications)

Condition B: V

CC = 4.0 V to 5.5 V,

CCB = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum

operating frequency, T

a = –20 to +75°C (regular specifications),

a = –40 to +85°C (wide-range specifications)

Condition C: V

CC = 2.7 V to 3.6 V,

CCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum

operating frequency, T

a = –20 to +75°C

Condition A

Condition B

Condition C

20 MHz

16 MHz

10 MHz

Item

Symbol

Min

Max

Min

Max

Min

Max

Unit

Test

Conditions

Clock cycle time

cyc

500

62.5

500

100

500

Figure 26.5

Clock high pulse

width

—

Figure 26.5

Clock low pulse

width

—

Clock rise time

—8

—10

—

Clock fall time

—8

—10

—

Oscillation settling

time at reset

(crystal)

OSC1

—

Figure 26.6

Oscillation settling

time in software

standby (crystal)

OSC2

8—

Figure 26.7

External clock

output stabilization

delay time

DEXT

500

—

500

—

500

—

µs

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