R4S2426 datasheet(22/1302 Pages) RENESAS

22 / 1302 page

Rev. 1.00 Sep. 19, 2008 Page xxii of xxviii

13.8.6 Mode Setting with Cascaded Connection ............................................................. 821

13.8.7 Module Stop Mode Setting ................................................................................... 821

13.8.8 Interrupts in Module Stop Mode........................................................................... 821

Section 14 Watchdog Timer (WDT) ................................................................. 823

14.1

Features.............................................................................................................................. 823

14.2

Input/Output Pin ................................................................................................................824

14.3

Register Descriptions ......................................................................................................... 825

14.3.1 Timer Counter (TCNT)......................................................................................... 825

14.3.2 Timer Control/Status Register (TCSR)................................................................. 825

14.3.3 Reset Control/Status Register (RSTCSR)............................................................. 827

14.4

Operation ........................................................................................................................... 828

14.4.1 Watchdog Timer Mode......................................................................................... 828

14.4.2 Interval Timer Mode............................................................................................. 829

14.5

Interrupt Source ................................................................................................................. 831

14.6

Usage Notes ....................................................................................................................... 831

14.6.1 Notes on Register Access ..................................................................................... 831

14.6.2 Contention between Timer Counter (TCNT) Write and Increment ...................... 833

14.6.3 Changing Value of CKS2 to CKS0 ...................................................................... 833

14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 833

14.6.5 Internal Reset in Watchdog Timer Mode.............................................................. 834

14.6.6 System Reset by

WDTOVF Signal....................................................................... 834

Section 15 Serial Communication Interface (SCI, IrDA) ................................. 835

15.1

Features.............................................................................................................................. 835

15.2

Input/Output Pins ...............................................................................................................838

15.3

Register Descriptions ......................................................................................................... 839

15.3.1 Receive Shift Register (RSR) ............................................................................... 840

15.3.2 Receive Data Register (RDR)............................................................................... 840

15.3.3 Transmit Data Register (TDR).............................................................................. 841

15.3.4 Transmit Shift Register (TSR) .............................................................................. 841

15.3.5 Serial Mode Register (SMR) ................................................................................ 841

15.3.6 Serial Control Register (SCR) .............................................................................. 845

15.3.7 Serial Status Register (SSR) ................................................................................. 850

15.3.8 Smart Card Mode Register (SCMR)..................................................................... 858

15.3.9 Bit Rate Register (BRR) ....................................................................................... 859

15.3.10 IrDA Control Register (IrCR)............................................................................... 866

15.3.11 Serial Extension Mode Register (SEMR) ............................................................. 867

15.4

Operation in Asynchronous Mode ..................................................................................... 869

15.4.1 Data Transfer Format............................................................................................ 869

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