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HD6433397CP Datasheet(PDF) 77 Page - Renesas Technology Corp |
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HD6433397CP Datasheet(HTML) 77 Page - Renesas Technology Corp |
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77 / 747 page ![]() 47 Before Execution of BCLR Instruction P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 Input/output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low Low DDR 00111111 DR 10000000 Execution of BCLR Instruction BCLR #0, @P4DDR ; Clear bit 0 in data direction register After Execution of BCLR Instruction P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 Input/output Output Output Output Output Output Output Output Input Pin state Low High Low Low Low Low Low High DDR 1 111111 0 DR 10000000 Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction. As a result, P4 0DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR are set to 1, making P4 7 and P46 output pins. |
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