HD6433397CP datasheet(32/747 Pages) RENESAS

32 / 747 page

Table 1.1

Features

Item

Specification

CPU

Two-way general register configuration

• Eight 16-bit registers, or

• Sixteen 8-bit registers

High-speed operation

• Maximum clock rate (ø clock): 16 MHz at 5 V, 12MHz at 4 V or 10 MHz

at 3 V

• 8- or 16-bit register-register add/subtract: 125 ns (16 MHz), 167 ns

(12MHz), 200 ns (10 MHz)

• 8 × 8-bit multiply: 875 ns (16 MHz), 1167 ns (12MHz), 1400 ns (10 MHz)

• 16 ÷ 8-bit divide: 875 ns (16 MHz), 1167 ns (12MHz), 1400 ns (10 MHz)

Streamlined, concise instruction set

• Instruction length: 2 or 4 bytes

• Register-register arithmetic and logic operations

• MOV instruction for data transfer between registers and memory

Instruction set features

• Multiply instruction (8 bits × 8 bits)

• Divide instruction (16 bits ÷ 8 bits)

• Bit-accumulator instructions

• Register-indirect specification of bit positions

Memory

• H8/3337Y, H8/3397: 60-kbyte ROM; 2-kbyte RAM

• H8/3336Y, H8/3396: 48-kbyte ROM; 2-kbyte RAM

• H8/3334Y, H8/3394: 32-kbyte ROM; 1-kbyte RAM

16-bit free-running

timer (1 channel)

• One 16-bit free-running counter (can also count external events)

• Two output-compare lines

• Four input capture lines (can be buffered)

8-bit timer

(2 channels)

Each channel has

• One 8-bit up-counter (can also count external events)

• Two time constant registers

PWM timer

(2 channels)

• Duty cycle can be set from 0 to 100%

• Resolution: 1/250

Watchdog timer

(WDT) (1 channel)

• Overflow can generate a reset or NMI interrupt

• Also usable as interval timer

HD6433397CP Datasheet(PDF) 32 Page - Renesas Technology Corp

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