32196 datasheet(46/1044 Pages) RENESAS

point Status Register (FPSR).

The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.

In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instruction.

Figure 2.3.1 Control Registers

2.1 CPU Registers

The M32R-FPU has 16 general-purpose registers, 6 control registers, an accumulator and a program counter.

The accumulator is of 56-bit configuration, and all other registers are of 32-bit configuration.

2.2 General-purpose Registers

The 16 general-purpose registers (R0–R15) are of 32-bit width and are used to retain data and base address, as

well as for integer calculations, floating-point operations, etc. R14 is used as the link register and R15 as the

stack pointer. The link register is used to store the return address when executing a subroutine call instruction.

The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are alternately represented by R15 depend-

ing on the value of the Stack Mode (SM) bit in the Processor Status Word Register (PSW).

Upon exiting the reset state, the value of the general-purpose registers is undefined.

Figure 2.2.1 General-purpose Registers

b31

R10

R11

R12

R13

R14 (Link register)

R15 (Stack pointer) (Note 1)

Note 1: The stack pointer functions as either the SPI or the SPU depending on

the value of the SM bit in the PSW.

b31

Backup PC

BPC

CR6

b31

PSW

CBR

SPI

SPU

CR0

CR1

CR2

CR3

Processor Status Word Register

Condition Bit Register

Interrupt Stack Pointer

User Stack Pointer

CRn

Notes: • CRn (n = 0-3, 6 and 7) denotes the control register number.

• The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.

• The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instruction.

Floating-point Status Register

FPSR

CR7

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