SH7265 datasheet(22/2024 Pages) RENESAS

22 / 2024 page

Rev. 1.00 Mar. 14, 2008 Page xxii of xxxvi

17.6

Usage Note ....................................................................................................................... 841

17.6.1

Module Standby Mode Setting ......................................................................... 841

17.6.2

Consecutive Data Transmission/Reception in SSU Slave Mode ...................... 841

Section 18 I

2C Bus Interface 3 (IIC3)................................................................843

18.1

Features............................................................................................................................. 843

18.2

Input/Output Pins.............................................................................................................. 845

18.3

Register Descriptions........................................................................................................ 846

18.3.1

2C Bus Control Register 1 (ICCR1)................................................................. 847

18.3.2

2C Bus Control Register 2 (ICCR2)................................................................. 850

18.3.3

2C Bus Mode Register (ICMR)........................................................................ 852

18.3.4

2C Bus Interrupt Enable Register (ICIER)....................................................... 854

18.3.5

2C Bus Status Register (ICSR)......................................................................... 856

18.3.6

Slave Address Register (SAR).......................................................................... 859

18.3.7

2C Bus Transmit Data Register (ICDRT) ........................................................ 859

18.3.8

2C Bus Receive Data Register (ICDRR).......................................................... 860

18.3.9

2C Bus Shift Register (ICDRS)........................................................................ 860

18.3.10

NF2CYC Register (NF2CYC).......................................................................... 861

18.4

Operation .......................................................................................................................... 862

18.4.1

2C Bus Format.................................................................................................. 862

18.4.2

Master Transmit Operation ............................................................................... 863

18.4.3

Master Receive Operation ................................................................................ 865

18.4.4

Slave Transmit Operation ................................................................................. 867

18.4.5

Slave Receive Operation................................................................................... 870

18.4.6

Clocked Synchronous Serial Format ................................................................ 871

18.4.7

Noise Filter ....................................................................................................... 875

18.4.8

Example of Use................................................................................................. 876

18.5

Interrupt Requests ............................................................................................................. 880

18.6

Bit Synchronous Circuit.................................................................................................... 881

18.7

Usage Notes ...................................................................................................................... 883

18.7.1

Note on Setting for Multi-Master Operation..................................................... 883

18.7.2

Note on Master Receive Mode ......................................................................... 883

18.7.3

Note on Setting ACKBT in Master Receive Mode........................................... 883

18.7.4

Note on the States of Bits MST and TRN when Arbitration is Lost................. 884

Section 19 Serial Sound Interface with FIFO (SSIF)........................................ 885

19.1

Features............................................................................................................................. 885

19.2

Input/Output Pins.............................................................................................................. 888

19.3

Register Description ......................................................................................................... 889

19.3.1

Control Register (SSICR) ................................................................................. 891

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