SH7265 datasheet(30/2024 Pages) RENESAS

30 / 2024 page

Rev. 1.00 Mar. 14, 2008 Page xxx of xxxvi

28.3.25

Panel-Output Horizontal Timing Setting Register for Output-Block

(MGR_MIXHTMG) ....................................................................................... 1453

28.3.26

Panel-Output Mixing Horizontal Valid Area Setting Register for Output

Block (MGR_MIXHS) ................................................................................... 1454

28.3.27

Panel-Output Vertical Timing Setting Register for Output-Block

(MGR_MIXVTMG) ....................................................................................... 1455

28.3.28

Panel-Output Mixing Vertical Valid Area Setting Register for Output

Block (MGR_MIXVS) ................................................................................... 1456

28.3.29

Graphics Block Output SYNC Position Setting Register (GR_VSDLY) ....... 1457

28.3.30

Video DAC Timing Setting Register (VDAC_TMC) .................................... 1458

28.4

Operation ........................................................................................................................ 1459

28.4.1

Input and Output Operations........................................................................... 1461

28.4.2

How to Use the DMA ..................................................................................... 1473

28.4.3

Blitter Operation ............................................................................................. 1478

28.4.4

Output Operations........................................................................................... 1530

28.4.5

Interrupts......................................................................................................... 1535

28.5

Appendix. VIDEO OUT (D/A Converter)...................................................................... 1540

28.5.1

Analog Output Current ................................................................................... 1540

28.5.2

Notes on Usage ............................................................................................... 1543

28.5.3

Application Example ...................................................................................... 1544

Section 29 AESOP .......................................................................................... 1545

29.1

Features........................................................................................................................... 1545

29.2

Input Format ................................................................................................................... 1546

29.3

Register Configuration.................................................................................................... 1547

29.3.1

Software Reset Register (SWRSR)................................................................. 1549

29.3.2

Encoding Processing Initialization Register (RPRSR) ................................... 1550

29.3.3

DMA Control Register (DMACR) ................................................................. 1551

29.3.4

DMA Transfer Register for DIN_RAM Buffer Write (DMADI) ................... 1552

29.3.5

DMA Transfer Register for DOUT_RAM Buffer Read (DMADO) .............. 1552

29.3.6

Event Mask Register (EVMSR)...................................................................... 1553

29.3.7

Event Clear Register (EVCLR) ...................................................................... 1554

29.3.8

Setting-Predetermined Register 1 (MBOTR) ................................................. 1555

29.3.9

Setting-Predetermined Register 2 (BACCR) .................................................. 1555

29.3.10

Setting-Predetermined Register 3 (ACESR)................................................... 1555

29.3.11

Audio Processing Information Setting Register (ADIFR) .............................. 1556

29.3.12

Setting-Predetermined Register 4 (TBRSR) ................................................... 1557

29.3.13

Header Setting Register (HEADR) ................................................................. 1557

29.3.14

ADTS Format Header Information Setting Register (ADTSR)...................... 1558

29.3.15

Setting-Predetermined Register 5 (MSS1R) ................................................... 1560

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