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4519 Datasheet(PDF) 91 Page - Renesas Technology Corp |
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4519 Datasheet(HTML) 91 Page - Renesas Technology Corp |
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91 / 272 page  4519 Group HARDWARE 1-78 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z CONTROL REGISTERS I13 I12 I11 I10 INT0 pin input control bit (Note 2) Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit Interrupt control register I1 R/W TAI1/TI1A at RAM back-up : state retained at reset : 00002 INT0 pin input disabled INT0 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI0 instruction) Rising waveform/“H” level (“H” level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected 0 1 0 1 0 1 0 1 Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) V13 V12 V11 V10 V23 V22 V21 V20 Serial I/O interrupt enable bit A/D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit Interrupt control register V2 at RAM back-up : 00002 at reset : 00002 0 1 0 1 0 1 0 1 Interrupt control register V1 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) 0 1 0 1 0 1 0 1 at RAM back-up : 00002 at reset : 00002 R/W TAV1/TV1A I23 I22 I21 I20 INT1 pin input control bit (Note 2) Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2) INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit Interrupt control register I2 R/W TAI2/TI2A at RAM back-up : state retained at reset : 00002 INT1 pin input disabled INT1 pin input enabled Falling waveform/“L” level (“L” level is recognized with the SNZI1 instruction) Rising waveform/“H” level (“H” level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected 0 1 0 1 0 1 0 1 Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12, I13 I22 and I23 are changed, the external interrupt request flag (EXF0, EXF1) may be set to “1”. R/W TAV2/TV2A CONTROL REGISTERS |
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