4519 datasheet(10/272 Pages) RENESAS

10 / 272 page

Rev.1.00

Aug 06, 2004

4519 Group

REJ09B0175-0100Z

List of figures

Fig. 2.3.15 Count start time and count time when operation starts (PS, T1, T2 and T3) 2-51

Fig. 2.3.16 Count start time and count time when operation starts (T4) ............................ 2-51

Fig. 2.4.1 A/D converter structure ............................................................................................. 2-52

Fig. 2.4.2 A/D conversion mode setting example .................................................................... 2-55

Fig. 2.4.3 Analog input external circuit example-1 .................................................................. 2-56

Fig. 2.4.4 Analog input external circuit example-2 .................................................................. 2-56

Fig. 2.4.5 A/D converter operating mode program example .................................................. 2-56

Fig. 2.5.1 Serial I/O block diagram ........................................................................................... 2-58

Fig. 2.5.2 Serial I/O connection example ................................................................................. 2-60

Fig. 2.5.3 Serial I/O register state when transfer .................................................................... 2-60

Fig. 2.5.4 Serial I/O transfer timing ........................................................................................... 2-61

Fig. 2.5.5 Setting example when a serial I/O of master side is not used .......................... 2-64

Fig. 2.5.6 Setting example when a serial I/O interrupt of slave side is used .................... 2-65

Fig. 2.6.1 Structure of reset pin and its peripherals, and power-on reset operation ......... 2-67

Fig. 2.6.2 Oscillation stabilizing time after system is released from reset .......................... 2-67

Fig. 2.6.3 Internal state at reset ................................................................................................ 2-68

Fig. 2.6.4 Internal state at reset ................................................................................................ 2-69

Fig. 2.7.1 Voltage drop detection circuit ................................................................................... 2-70

Fig. 2.7.2 Voltage drop detection circuit operation waveform example ............................... 2-70

Fig. 2.8.1 State transition ............................................................................................................ 2-71

Fig. 2.8.2 Start condition identified example ............................................................................ 2-73

Fig. 2.9.1 Structure of clock control circuit .............................................................................. 2-79

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