4524 datasheet(10/310 Pages) RENESAS

10 / 310 page

Rev.2.00

Aug, 06 2004

4524 Group

REJ09B0107-0200Z

Fig. 2.3.1 Peripheral circuit example ............................................................................................ 39

Fig. 2.3.2 Timer 4 operation .......................................................................................................... 40

Fig. 2.3.3 Watchdog timer function ............................................................................................... 41

Fig. 2.3.4 Constant period measurement setting example ........................................................ 42

Fig. 2.3.5 CNTR0 output setting example .................................................................................... 43

Fig. 2.3.6 CNTR0 input setting example ...................................................................................... 44

Fig. 2.3.7 Timer start by external input setting example .......................................................... 45

Fig. 2.3.8 PWM output control setting example ......................................................................... 46

Fig. 2.3.9 Constant period counter by timer 5 setting example ............................................... 47

Fig. 2.3.10 Watchdog timer setting example ............................................................................... 48

Fig. 2.4.1 A/D converter structure ................................................................................................ 50

Fig. 2.4.2 A/D conversion mode setting example ....................................................................... 53

Fig. 2.4.3 Analog input external circuit example-1 ..................................................................... 54

Fig. 2.4.4 Analog input external circuit example-2 ..................................................................... 54

Fig. 2.4.5 A/D converter operating mode program example ..................................................... 54

Fig. 2.5.1 Serial I/O block diagram .............................................................................................. 56

Fig. 2.5.2 Serial I/O connection example .................................................................................... 59

Fig. 2.5.3 Serial I/O register state when transfer ....................................................................... 59

Fig. 2.5.4 Serial I/O transfer timing .............................................................................................. 60

Fig. 2.5.5 Setting example when a serial I/O of master side is not used ............................. 63

Fig. 2.5.6 Setting example when a serial I/O interrupt of slave side is used ....................... 64

Fig. 2.6.1 LCD clock control circuit structure .............................................................................. 66

Fig. 2.6.2 LCD RAM map .............................................................................................................. 67

Fig. 2.6.3 LCD display panel example ......................................................................................... 69

Fig. 2.6.4 Segment assignment example ..................................................................................... 69

Fig. 2.6.5 LCD RAM assignment example .................................................................................. 69

Fig. 2.6.6 Initial setting example ................................................................................................... 70

Fig. 2.7.1 Structure of reset pin and its peripherals,, and power-on reset operation ........... 72

Fig. 2.7.2 Oscillation stabilizing time after system is released from reset ............................. 72

Fig. 2.7.3 Internal state at reset ................................................................................................... 73

Fig. 2.7.4 Internal state at reset ................................................................................................... 74

Fig. 2.8.1 Voltage drop detection circuit ...................................................................................... 75

Fig. 2.8.2 Voltage drop detection circuit operation waveform example .................................. 75

Fig. 2.8.3 VDD and VRST ....................................................................................................................................................................................................... 76

Fig. 2.9.1 State transition ............................................................................................................... 77

Fig. 2.9.2 Start condition identified example ............................................................................... 80

Fig. 2.9.3 Software setting example ............................................................................................. 85

Fig. 2.10.1 Switch to ceramic oscillation/RC oscillation ............................................................ 87

Fig. 2.10.2 Handling of XIN and XOUT when operating on-chip oscillator ................................. 87

Fig. 2.10.3 Ceramic resonator external circuit ............................................................................ 88

Fig. 2.10.4 External RC oscillation circuit ................................................................................... 88

Fig. 2.10.5 External clock input circuit ......................................................................................... 88

Fig. 2.10.6 External quartz-crystal circuit .................................................................................... 88

Fig. 2.10.7 Structure of clock control circuit ............................................................................... 89

List of figures

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