7540 datasheet(318/366 Pages) RENESAS

318 / 366 page

3-96

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

APPENDIX

7540 Group

3.4 Countermeasures against noise

(2) Installing oscillator away from signal lines where potential levels change frequently

Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential

levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines

which are sensitive to noise.

q Reason

Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect

other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms

may be deformed, which causes a microcomputer failure or a program runaway.

3) Oscillator protection using VSS pattern

As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the

position (on the component side) where an oscillator is mounted.

Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides,

separate this VSS pattern from other VSS patterns.

XIN

XOUT

VSS

CNTR

Do not cross

N.G.

XIN

XOUT

VSS

An example of VSS patterns on the

underside of a printed circuit board

Oscillator wiring

pattern example

Separate the VSS line for oscillation from other VSS lines

3.4.5 Setup for I/O ports

Setup I/O ports using hardware and software as

follows:

• Connect a resistor of 100

Ω or more to an

I/O port in series.

• As for an input port, read data several times

by a program for checking whether input

levels are equal or not.

• As for an output port, since the output data

may reverse because of noise, rewrite data

to its port latch at fixed periods.

• Rewrite data to direction registers and pull-

up control registers at fixed periods.

Note: When a direction register is set for input port

again at fixed periods, a several-nanosecond

short pulse may be output from this port. If this

is undesirable, connect a capacitor to this port

to remove the noise pulse.

Fig. 3.4.10 VSS pattern on the underside of an oscillator

Fig. 3.4.9 Wiring of signal lines where potential

levels change frequently

Fig. 3.4.11 Setup for I/O ports

Direction register

Port latch

Data bus

I/O port

pins

Noise

N.G.

O.K.

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