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H83062 Datasheet(PDF) 13 Page - Renesas Technology Corp |
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H83062 Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 1021 page ![]() Rev. 6.00 Mar 18, 2005 page xiii of xlviii Section 4 Exception Handling ......................................................................................... 87 4.1 Overview........................................................................................................................... 87 4.1.1 Exception Handling Types and Priority............................................................... 87 4.1.2 Exception Handling Operation ............................................................................ 87 4.1.3 Exception Vector Table ....................................................................................... 88 4.2 Reset90 4.2.1 Overview.............................................................................................................. 90 4.2.2 Reset Sequence .................................................................................................... 90 4.2.3 Interrupts after Reset............................................................................................ 93 4.3 Interrupts........................................................................................................................... 94 4.4 Trap Instruction ................................................................................................................ 94 4.5 Stack Status after Exception Handling.............................................................................. 95 4.6 Notes on Stack Usage ....................................................................................................... 96 Section 5 Interrupt Controller .......................................................................................... 99 5.1 Overview........................................................................................................................... 99 5.1.1 Features................................................................................................................ 99 5.1.2 Block Diagram..................................................................................................... 100 5.1.3 Pin Configuration ................................................................................................ 101 5.1.4 Register Configuration......................................................................................... 101 5.2 Register Descriptions........................................................................................................ 101 5.2.1 System Control Register (SYSCR) ...................................................................... 101 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 102 5.2.3 IRQ Status Register (ISR).................................................................................... 108 5.2.4 IRQ Enable Register (IER) .................................................................................. 109 5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 110 5.3 Interrupt Sources............................................................................................................... 111 5.3.1 External Interrupts ............................................................................................... 111 5.3.2 Internal Interrupts ................................................................................................ 112 5.3.3 Interrupt Exception Handling Vector Table......................................................... 112 5.4 Interrupt Operation ........................................................................................................... 116 5.4.1 Interrupt Handling Process .................................................................................. 116 5.4.2 Interrupt Exception Handling Sequence .............................................................. 121 5.4.3 Interrupt Response Time...................................................................................... 122 5.5 Usage Notes ...................................................................................................................... 123 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 123 5.5.2 Instructions that Inhibit Interrupts ....................................................................... 124 5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 124 |
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