H83062 datasheet(28/1021 Pages) RENESAS

28 / 1021 page

Rev. 6.00 Mar 18, 2005 page xxviii of xlviii

Figures

Section 1 Overview

Figure 1.1

Block Diagram.....................................................................................................

Figure 1.2

Pin Arrangement of H8/3062F-ZTAT R-Mask Version,

H8/3062 Masked ROM Version, H8/3061 Masked ROM Version,

and H8/3060 Masked ROM Version (FP-100B or TFP-100B Package,

Top View)............................................................................................................

Figure 1.3

Pin Arrangement of H8/3062F-ZTAT R-Mask Version,

H8/3062 Masked ROM Version, H8/3061 Masked ROM Version,

and H8/3060 Masked ROM Version (FP-100A Package, Top View) .................

Figure 1.4

Pin Arrangement of H8/3064F-ZTAT B-Mask Version,

H8/3062F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version,

H8/3062 Masked ROM B-Mask Version, H8/3061 Masked ROM B-Mask Version,

and H8/3060 Masked ROM B-Mask Version (FP-100B or TFP-100B Package,

Top View)............................................................................................................

Figure 1.5

Pin Arrangement of H8/3064F-ZTAT B-Mask Version,

H8/3062F-ZTAT B-Mask Version, H8/3064 Masked ROM B-Mask Version,

H8/3062 Masked ROM B-Mask Version, H8/3061 Masked ROM B-Mask Version,

and H8/3060 Masked ROM B-Mask Version (FP-100A Package, Top View) ...

Figure 1.6

H8/3062F-ZTAT B-Mask Version, H8/3064F-ZTAT B-Mask Version,

and On-Chip Masked ROM B-Mask Versions ....................................................

Figure 1.7

Example of Board Pattern Providing for External Capacitor...............................

Section 2 CPU

Figure 2.1

CPU Operating Modes.........................................................................................

Figure 2.2

Memory Map .......................................................................................................

Figure 2.3

CPU Registers......................................................................................................

Figure 2.4

Usage of General Registers..................................................................................

Figure 2.5

Stack ....................................................................................................................

Figure 2.6

General Register Data Formats............................................................................

Figure 2.7

General Register Data Formats............................................................................

Figure 2.8

Memory Data Formats .........................................................................................

Figure 2.9

Instruction Formats..............................................................................................

Figure 2.10

Memory-Indirect Branch Address Specification .................................................

Figure 2.11

Processing States .................................................................................................

Figure 2.12

Classification of Exception Sources ....................................................................

Figure 2.13

State Transitions ..................................................................................................

Figure 2.14

Stack Structure after Exception Handling............................................................

H83062 Datasheet(PDF) 28 Page - Renesas Technology Corp

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