H83069RF datasheet(107/1003 Pages) RENESAS

107 / 1003 page

Rev. 5.0, 09/04, page 85 of 978

5.1.3

Pin Configuration

Table 5.1 lists the interrupt pins.

Table 5.1

Interrupt Pins

Name

Abbreviation

I/O

Function

Nonmaskable interrupt

NMI

Input Nonmaskable interrupt*, rising edge or

falling edge selectable

External interrupt request 5 to 0

IRQ

5 to IRQ0

Input Maskable interrupts, falling edge or level

sensing selectable

Note:

NMI input is sometimes disabled when flash memory is being programmed or erased.

For details see section 18.4.5, Flash Vector Address Control Register (FVACR).

5.1.4

Table 5.2 lists the registers of the interrupt controller.

Table 5.2

Interrupt Controller Registers

Address*

Name

Abbreviation

R/W

Initial Value

H'EE012

System control register

SYSCR

R/W

H'09

H'EE014

IRQ sense control register

ISCR

R/W

H'00

H'EE015

IRQ enable register

IER

R/W

H'00

H'EE016

IRQ status register

ISR

R/(W)*

H'00

H'EE018

Interrupt priority register A

IPRA

R/W

H'00

H'EE019

Interrupt priority register B

IPRB

R/W

H'00

Notes: 1. Lower 20 bits of the address in advanced mode.

2. Only 0 can be written, to clear flags.

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