H83069RF datasheet(16/1003 Pages) RENESAS

16 / 1003 page

Rev. 5.0, 09/04, page xii of xviii

10.4.6 Input Capture Setting ........................................................................................... 400

10.5

Interrupt ............................................................................................................................ 401

10.5.1 Interrupt Sources.................................................................................................. 401

10.5.2 A/D Converter Activation.................................................................................... 402

10.6

8-Bit Timer Application Example..................................................................................... 402

10.7

Usage Notes ...................................................................................................................... 403

10.7.1 Contention between 8TCNT Write and Clear...................................................... 403

10.7.2 Contention between 8TCNT Write and Increment .............................................. 404

10.7.3 Contention between TCOR Write and Compare Match ...................................... 405

10.7.4 Contention between TCOR Read and Input Capture ........................................... 406

10.7.5 Contention between Counter Clearing by Input Capture and

Counter Increment ............................................................................................... 407

10.7.6 Contention between TCOR Write and Input Capture .......................................... 408

10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

(Cascaded Connection) ........................................................................................ 409

10.7.8 Contention between Compare Matches A and B ................................................. 410

10.7.9 8TCNT Operation and Internal Clock Source Switchover .................................. 410

Section 11 Programmable Timing Pattern Controller (TPC) ............................413

11.1

Overview........................................................................................................................... 413

11.1.1 Features................................................................................................................ 413

11.1.2 Block Diagram ..................................................................................................... 414

11.1.3 TPC Pins .............................................................................................................. 415

11.1.4 Registers............................................................................................................... 416

11.2

Register Descriptions ........................................................................................................ 417

11.2.1 Port A Data Direction Register (PADDR) ........................................................... 417

11.2.2 Port A Data Register (PADR) .............................................................................. 417

11.2.3 Port B Data Direction Register (PBDDR)............................................................ 418

11.2.4 Port B Data Register (PBDR) .............................................................................. 418

11.2.5 Next Data Register A (NDRA) ............................................................................ 419

11.2.6 Next Data Register B (NDRB)............................................................................. 421

11.2.7 Next Data Enable Register A (NDERA).............................................................. 423

11.2.8 Next Data Enable Register B (NDERB) .............................................................. 424

11.2.9 TPC Output Control Register (TPCR) ................................................................. 425

11.2.10 TPC Output Mode Register (TPMR) ................................................................... 428

11.3

Operation .......................................................................................................................... 430

11.3.1 Overview.............................................................................................................. 430

11.3.2 Output Timing...................................................................................................... 431

11.3.3 Normal TPC Output............................................................................................. 432

11.3.4 Non-Overlapping TPC Output ............................................................................. 434

11.3.5 TPC Output Triggering by Input Capture ............................................................ 436

11.4

Usage Notes ...................................................................................................................... 437

11.4.1 Operation of TPC Output Pins ............................................................................. 437

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