H83069RF datasheet(132/1003 Pages) RENESAS

132 / 1003 page

Rev. 5.0, 09/04, page 110 of 978

5.5.2

Instructions that Inhibit Interrupts

The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after

determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is

currently executing one of these interrupt-inhibiting instructions, however, when the instruction is

completed the CPU always continues by executing the next instruction.

5.5.3

Interrupts during EEPMOV Instruction Execution

The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.

When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the

transfer is completed, not even NMI.

When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are

not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at

a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.

Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:

L1: EEPMOV.W

MOV.W R4,R4

BNE

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